soc/intel/xeon_sp/cpx: Don't use SCI define
Continue preparations for common ACPI code. Add code from skx and common/acpi to check the SCI register instead of using a define. Change-Id: I6b638d28775320894a6ab24ef486e67c181591eb Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45844 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -25,11 +25,41 @@
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#include "chip.h"
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#define SCI_INT_NUM 9
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static int acpi_sci_irq(void)
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{
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int sci_irq = 9;
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uint32_t scis;
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scis = soc_read_sci_irq_select();
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scis &= SCI_IRQ_SEL;
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scis >>= SCI_IRQ_ADJUST;
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/* Determine how SCI is routed. */
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switch (scis) {
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case SCIS_IRQ9:
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case SCIS_IRQ10:
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case SCIS_IRQ11:
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sci_irq = scis - SCIS_IRQ9 + 9;
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break;
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case SCIS_IRQ20:
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case SCIS_IRQ21:
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case SCIS_IRQ22:
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case SCIS_IRQ23:
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sci_irq = scis - SCIS_IRQ20 + 20;
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break;
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default:
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printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
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sci_irq = 9;
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break;
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}
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printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
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return sci_irq;
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}
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static unsigned long acpi_madt_irq_overrides(unsigned long current)
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{
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int sci = SCI_INT_NUM;
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int sci = acpi_sci_irq();
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uint16_t flags = MP_IRQ_TRIGGER_LEVEL;
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/* INT_SRC_OVR */
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@ -103,7 +133,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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const uint16_t pmbase = ACPI_BASE_ADDRESS;
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fadt->header.revision = get_acpi_table_revision(FADT);
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fadt->sci_int = SCI_INT_NUM;
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fadt->sci_int = acpi_sci_irq();
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fadt->pm1a_evt_blk = pmbase + PM1_STS;
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fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
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@ -42,6 +42,16 @@ int soc_madt_sci_irq_polarity(int sci)
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return MP_IRQ_POLARITY_HIGH;
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}
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uint32_t soc_read_sci_irq_select(void)
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{
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struct device *dev = PCH_DEV_PMC;
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if (!dev)
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return 0;
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return pci_read_config32(dev, PMC_ACPI_CNT);
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}
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/*
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* Currently called in southbridge_inject_dsdt(). Change to soc_southbridge_inject_dsdt()
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* with a call from the common/function or find another way to call this at the correct place
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