diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 25eb94fed6..89128659bb 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -137,11 +137,11 @@ static void sata_init(struct device *dev)
 		reg32 |= 1 << 5;     /* BWG step 9 */
 		reg32 |= 1 << 18;    /* BWG step 10 */
 		reg32 |= 1 << 29;    /* BWG step 11 */
-#if CONFIG_INTEL_LYNXPOINT_LP
-		reg32 &= ~((1 << 31) | (1 << 30));
-		reg32 |= 1 << 23;
-		reg32 |= 1 << 24;    /* Disable listen mode (hotplug) */
-#endif
+		if (pch_is_lp()) {
+			reg32 &= ~((1 << 31) | (1 << 30));
+			reg32 |= 1 << 23;
+			reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
+		}
 		pci_write_config32(dev, 0x98, reg32);
 
 		/* Setup register 9Ch */
@@ -162,9 +162,8 @@ static void sata_init(struct device *dev)
 		reg32 = read32(abar + 0x00);
 		reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
 		reg32 &= ~0x00020060; // clear SXS+EMS+PMS
-#if CONFIG_INTEL_LYNXPOINT_LP
-		reg32 |= (1 << 18);   // SAM: SATA AHCI MODE ONLY
-#endif
+		if (pch_is_lp())
+			reg32 |= (1 << 18);   // SAM: SATA AHCI MODE ONLY
 		write32(abar + 0x00, reg32);
 		/* PI (Ports implemented) */
 		write32(abar + 0x0c, config->sata_port_map);
@@ -172,12 +171,11 @@ static void sata_init(struct device *dev)
 		(void) read32(abar + 0x0c); /* Read back 2 */
 		/* CAP2 (HBA Capabilities Extended)*/
 		reg32 = read32(abar + 0x24);
-#if CONFIG_INTEL_LYNXPOINT_LP
 		/* Enable DEVSLP */
-		reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
-#else
-		reg32 &= ~0x00000002;
-#endif
+		if (pch_is_lp())
+			reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
+		else
+			reg32 &= ~0x00000002;
 		write32(abar + 0x24, reg32);
 	} else {
 		printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
@@ -239,11 +237,10 @@ static void sata_init(struct device *dev)
 	/* Power Optimizer */
 
 	/* Step 1 */
-#if CONFIG_INTEL_LYNXPOINT_LP
-	sir_write(dev, 0x64, 0x883c9003);
-#else
-	sir_write(dev, 0x64, 0x883c9001);
-#endif
+	if (pch_is_lp())
+		sir_write(dev, 0x64, 0x883c9003);
+	else
+		sir_write(dev, 0x64, 0x883c9001);
 
 	/* Step 2: SIR 68h[15:0] = 880Ah */
 	reg32 = sir_read(dev, 0x68);
@@ -268,10 +265,10 @@ static void sata_init(struct device *dev)
 
 	/* Clock Gating */
 	sir_write(dev, 0x70, 0x3f00bf1f);
-#if CONFIG_INTEL_LYNXPOINT_LP
-	sir_write(dev, 0x54, 0xcf000f0f);
-	sir_write(dev, 0x58, 0x00190000);
-#endif
+	if (pch_is_lp()) {
+		sir_write(dev, 0x54, 0xcf000f0f);
+		sir_write(dev, 0x58, 0x00190000);
+	}
 
 	reg32 = pci_read_config32(dev, 0x300);
 	reg32 |= (1 << 17) | (1 << 16);