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soc/amd/cezanne: remove UART2/3 AOAC device offsets 

UART2 and UART3 don't exist on Cezanne which now has been verified, so
remove the corresponding AOAC offsets.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-02-02 16:15:17 +01:00
parent 4c4a360018
commit 70f1af8934
1 changed files with 0 additions and 2 deletions
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2
src/soc/amd/cezanne/include/soc/southbridge.h
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@ -22,9 +22,7 @@
#define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_I2C5 10
#define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART0 11
#define FCH_AOAC_DEV_UART1 12 #define FCH_AOAC_DEV_UART1 12
#define FCH_AOAC_DEV_UART2 16
#define FCH_AOAC_DEV_AMBA 17 #define FCH_AOAC_DEV_AMBA 17
#define FCH_AOAC_DEV_UART3 26
#define FCH_AOAC_DEV_ESPI 27 #define FCH_AOAC_DEV_ESPI 27
/* IO 0xf0 NCP Error */ /* IO 0xf0 NCP Error */