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soc/mediatek/mt8188: Enable mfgpll properly and fix SPMI muxes 

Some of the pll settings are incorrect, which cause problems in GPU
after booting into kernel.

- MFGPLL opp_ck_en bit isn't located at MFGPLL_CON1, so we need to fix
  it to enable MFGPLL properly.
- Switch SPMI clock muxes to 260M to avoid kernel hang while probing
  SPMI kernel driver.

TEST=GPU bringup correctly.
BUG=b:233720142

Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Change-Id: I971109a5f72e3307899daaf5a5f26022124b559b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67355
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit is contained in:
Johnson Wang 2022-08-30 16:56:43 +08:00 committed by Felix Held
parent 60ef19bcf3
commit 70f30afa89
1 changed files with 3 additions and 4 deletions
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7
src/soc/mediatek/mt8188/pll.c
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@ -319,9 +319,9 @@ static const struct mux_sel mux_sels[] = {
{ .id = TOP_VDEC_SEL, .sel = 1 }, /* 1: mainpll_d5_d2 */
{ .id = TOP_PWM_SEL, .sel = 3 }, /* 3: univpll_d6_d4 */
{ .id = TOP_MCUPM_SEL, .sel = 1 }, /* 1: mainpll_d6_d2 */
{ .id = TOP_SPMI_P_MST_SEL, .sel = 7 }, /* 7: mainpll_d7_d8 */
{ .id = TOP_SPMI_P_MST_SEL, .sel = 3 }, /* 7: mainpll_d7_d8 */
/* CLK_CFG_14 */
{ .id = TOP_SPMI_M_MST_SEL, .sel = 7 }, /* 7: mainpll_d7_d8 */
{ .id = TOP_SPMI_M_MST_SEL, .sel = 3 }, /* 7: mainpll_d7_d8 */
{ .id = TOP_DVFSRC_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_TL_SEL, .sel = 2 }, /* 2: mainpll_d4_d4 */
{ .id = TOP_AES_MSDCFDE_SEL, .sel = 5 }, /* 5: univpll_d6 */
@ -522,8 +522,7 @@ void mt_pll_init(void)
}
/* disable mfg_ck_en[20], enable mfg_opp_ck_en[2] */
clrbits32(&mtk_apmixed->mfgpll_con0, 0x1 << 20);
setbits32(&mtk_apmixed->mfgpll_con1, 0x1 << 2);
clrsetbits32(&mtk_apmixed->mfgpll_con0, BIT(20), BIT(2));
/* xPLL Frequency Set */
for (i = 0; i < ARRAY_SIZE(rates); i++)