diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 6553f29077..cd722f540c 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -166,6 +166,8 @@ static void configure_emttm_tables(void)
 	wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
 }
 
+#define IA32_PECI_CTL		0x5a0
+
 static void configure_misc(const int eist, const int tm2, const int emttm)
 {
 	msr_t msr;
@@ -208,6 +210,13 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
 		msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
 		wrmsr(IA32_MISC_ENABLE, msr);
 	}
+
+	/* Enable PECI
+	   WARNING: due to Erratum AW67 described in Intel document #318733
+	   the microcode must be updated before this MSR is written to. */
+	msr = rdmsr(IA32_PECI_CTL);
+	msr.lo |= 1;
+	wrmsr(IA32_PECI_CTL, msr);
 }
 
 #define PIC_SENS_CFG	0x1aa