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imgtec/pistachio: Add SOC_REGISTERS memory region 

When used with a U-boot payload it will need this region
identity mapped also, so we're defining it in preparation
for that functionality.

Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12768
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Ionela Voinescu 2015-07-24 14:29:06 +01:00 committed by Stefan Reinauer
parent 1136447a37
commit 7100cf2b40
3 changed files with 8 additions and 0 deletions
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2
src/arch/mips/include/arch/memlayout.h
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@ -26,4 +26,6 @@
#define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K) #define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K)
#define SOC_REGISTERS(addr, size) REGION(soc_registers, addr, size, 4)
#endif /* __ARCH_MEMLAYOUT_H */ #endif /* __ARCH_MEMLAYOUT_H */

4
src/include/symbols.h
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@ -72,6 +72,10 @@ extern u8 _dma_coherent[];
extern u8 _edma_coherent[]; extern u8 _edma_coherent[];
#define _dma_coherent_size (_edma_coherent - _dma_coherent) #define _dma_coherent_size (_edma_coherent - _dma_coherent)
extern u8 _soc_registers[];
extern u8 _esoc_registers[];
#define _soc_registers_size (_esoc_registers - _soc_registers)
extern u8 _framebuffer[]; extern u8 _framebuffer[];
extern u8 _eframebuffer[]; extern u8 _eframebuffer[];
#define _framebuffer_size (_eframebuffer - _framebuffer) #define _framebuffer_size (_eframebuffer - _framebuffer)

2
src/soc/imgtec/pistachio/include/soc/memlayout.ld
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@ -29,6 +29,8 @@ SECTIONS
POSTRAM_CBFS_CACHE(0x00200000, 512K) POSTRAM_CBFS_CACHE(0x00200000, 512K)
RAMSTAGE(0x00280000, 128K) RAMSTAGE(0x00280000, 128K)
/* 0x18100000 -> 0x18540000 */
SOC_REGISTERS(0x18100000, 0x440000)
/* /*
* GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock
* and then through the identity mapping in ROM stage. * and then through the identity mapping in ROM stage.