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mb/intel/d510mo: Add missing GPIO and GPEN 

Change-Id: I56c0a55d57d8beabcb33cf1984b037556a71a8b9
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13452
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Damien Zammit 2016-01-26 13:52:33 +11:00 committed by Martin Roth
parent 51fdb9256a
commit 7102d005b9
2 changed files with 2 additions and 0 deletions
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1
src/mainboard/intel/d510mo/devicetree.cb
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@ -36,6 +36,7 @@ chip northbridge/intel/pineview # Northbridge
register "ide_enable_primary" = "0x1" register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0" register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0" register "sata_ahci" = "0x0"
register "gpe0_en" = "0x20000040"
device pci 1b.0 on end # Audio device pci 1b.0 on end # Audio
device pci 1c.0 on end # PCIe 1 device pci 1c.0 on end # PCIe 1

1
src/mainboard/intel/d510mo/romstage.c
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@ -50,6 +50,7 @@ static void mb_gpio_init(void)
outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
outl(0x000000fe, DEFAULT_GPIOBASE + 0x30); outl(0x000000fe, DEFAULT_GPIOBASE + 0x30);
outl(0x0000007e, DEFAULT_GPIOBASE + 0x34); outl(0x0000007e, DEFAULT_GPIOBASE + 0x34);