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K8_4RANK to QRANK 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu 2006-10-05 06:59:56 +00:00
parent ab9f49d2fa
commit 7110f9261f
18 changed files with 31 additions and 33 deletions
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2
src/mainboard/agami/aruma/cache_as_ram_auto.c
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@ -8,7 +8,7 @@
#endif #endif
//use by raminit //use by raminit
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
//used by incoherent_ht //used by incoherent_ht
//#define K8_SCAN_PCI_BUS 1 //#define K8_SCAN_PCI_BUS 1

2
src/mainboard/amd/serengeti_leopard/auto.c
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@ -129,7 +129,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
} }
//#include "northbridge/amd/amdk8/setup_resource_map.c" //#include "northbridge/amd/amdk8/setup_resource_map.c"
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#if 0 #if 0

2
src/mainboard/sunw/ultra40/auto.c
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@ -91,7 +91,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#if 0 #if 0

2
src/mainboard/sunw/ultra40/cache_as_ram_auto.c
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@ -6,7 +6,7 @@
//#define K8_SCAN_PCI_BUS 1 //#define K8_SCAN_PCI_BUS 1
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1

2
src/mainboard/tyan/s2850/cache_as_ram_auto.c
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@ -79,8 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"

2
src/mainboard/tyan/s2875/cache_as_ram_auto.c
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@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"

2
src/mainboard/tyan/s2880/cache_as_ram_auto.c
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@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/resourcemap.c"

2
src/mainboard/tyan/s2881/auto.c
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@ -107,7 +107,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
} }
//#include "northbridge/amd/amdk8/setup_resource_map.c" //#include "northbridge/amd/amdk8/setup_resource_map.c"
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"

2
src/mainboard/tyan/s2882/auto.c
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@ -108,7 +108,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
} }
#include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/setup_resource_map.c"
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"

2
src/mainboard/tyan/s2882/cache_as_ram_auto.c
View File

@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/resourcemap.c"

2
src/mainboard/tyan/s2885/auto.c
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@ -106,7 +106,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
} }
//#include "northbridge/amd/amdk8/setup_resource_map.c" //#include "northbridge/amd/amdk8/setup_resource_map.c"
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#if 0 #if 0

2
src/mainboard/tyan/s2891/auto.c
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@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"

2
src/mainboard/tyan/s2892/auto.c
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@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"

2
src/mainboard/tyan/s2895/auto.c
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@ -91,7 +91,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#if 0 #if 0

2
src/mainboard/tyan/s4880/cache_as_ram_auto.c
View File

@ -83,7 +83,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"

2
src/mainboard/tyan/s4882/auto.c
View File

@ -115,7 +115,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
} }
#include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/setup_resource_map.c"
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#if 0 #if 0
#define ENABLE_APIC_EXT_ID 1 #define ENABLE_APIC_EXT_ID 1

2
src/mainboard/tyan/s4882/cache_as_ram_auto.c
View File

@ -92,7 +92,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define K8_4RANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"

30
src/northbridge/amd/amdk8/raminit.c
View File

@ -17,8 +17,8 @@
# error "CONFIG_LB_MEM_TOPK must be a power of 2" # error "CONFIG_LB_MEM_TOPK must be a power of 2"
#endif #endif
#ifndef K8_4RANK_DIMM_SUPPORT #ifndef QRANK_DIMM_SUPPORT
#define K8_4RANK_DIMM_SUPPORT 0 #define QRANK_DIMM_SUPPORT 0
#endif #endif
#if defined (__GNUC__) #if defined (__GNUC__)
@ -631,7 +631,7 @@ struct dimm_size {
unsigned long side2; unsigned long side2;
unsigned long rows; unsigned long rows;
unsigned long col; unsigned long col;
#if K8_4RANK_DIMM_SUPPORT == 1 #if QRANK_DIMM_SUPPORT == 1
unsigned long rank; unsigned long rank;
#endif #endif
}; };
@ -645,7 +645,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
sz.side2 = 0; sz.side2 = 0;
sz.rows = 0; sz.rows = 0;
sz.col = 0; sz.col = 0;
#if K8_4RANK_DIMM_SUPPORT == 1 #if QRANK_DIMM_SUPPORT == 1
sz.rank = 0; sz.rank = 0;
#endif #endif
@ -689,7 +689,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
if ((value != 2) && (value != 4 )) { if ((value != 2) && (value != 4 )) {
goto val_err; goto val_err;
} }
#if K8_4RANK_DIMM_SUPPORT == 1 #if QRANK_DIMM_SUPPORT == 1
sz.rank = value; sz.rank = value;
#endif #endif
@ -718,7 +718,7 @@ hw_err:
sz.side2 = 0; sz.side2 = 0;
sz.rows = 0; sz.rows = 0;
sz.col = 0; sz.col = 0;
#if K8_4RANK_DIMM_SUPPORT == 1 #if QRANK_DIMM_SUPPORT == 1
sz.rank = 0; sz.rank = 0;
#endif #endif
out: out:
@ -766,7 +766,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz
/* Set the appropriate DIMM base address register */ /* Set the appropriate DIMM base address register */
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
#if K8_4RANK_DIMM_SUPPORT == 1 #if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) { if(sz.rank == 4) {
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1); pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
@ -777,7 +777,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz
if (base0) { if (base0) {
dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
dch |= DCH_MEMCLK_EN0 << index; dch |= DCH_MEMCLK_EN0 << index;
#if K8_4RANK_DIMM_SUPPORT == 1 #if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) { if(sz.rank == 4) {
dch |= DCH_MEMCLK_EN0 << (index + 2); dch |= DCH_MEMCLK_EN0 << (index + 2);
} }
@ -800,7 +800,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4)); map &= ~(0xf << (index * 4));
#if K8_4RANK_DIMM_SUPPORT == 1 #if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) { if(sz.rank == 4) {
map &= ~(0xf << ( (index + 2) * 4)); map &= ~(0xf << ( (index + 2) * 4));
} }
@ -811,7 +811,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
if (sz.side1 >= (25 +3)) { if (sz.side1 >= (25 +3)) {
if(is_cpu_pre_d0()) { if(is_cpu_pre_d0()) {
map |= (sz.side1 - (25 + 3)) << (index *4); map |= (sz.side1 - (25 + 3)) << (index *4);
#if K8_4RANK_DIMM_SUPPORT == 1 #if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) { if(sz.rank == 4) {
map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4); map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
} }
@ -819,7 +819,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
} }
else { else {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4); map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
#if K8_4RANK_DIMM_SUPPORT == 1 #if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) { if(sz.rank == 4) {
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4); map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
} }
@ -1538,7 +1538,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
} }
#if 0 #if 0
//down speed for full load 4 rank support //down speed for full load 4 rank support
#if K8_4RANK_DIMM_SUPPORT #if QRANK_DIMM_SUPPORT
if(dimm_mask == (3|(3<<DIMM_SOCKETS)) ) { if(dimm_mask == (3|(3<<DIMM_SOCKETS)) ) {
int ranks = 4; int ranks = 4;
for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) {
@ -1804,7 +1804,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa
{ {
uint32_t dcl; uint32_t dcl;
int value; int value;
#if K8_4RANK_DIMM_SUPPORT == 1 #if QRANK_DIMM_SUPPORT == 1
int rank; int rank;
#endif #endif
int dimm; int dimm;
@ -1813,7 +1813,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa
return -1; return -1;
} }
#if K8_4RANK_DIMM_SUPPORT == 1 #if QRANK_DIMM_SUPPORT == 1
rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */ rank = spd_read_byte(ctrl->channel0[i], 5); /* number of physical banks */
if (rank < 0) { if (rank < 0) {
return -1; return -1;
@ -1821,7 +1821,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa
#endif #endif
dimm = 1<<(DCL_x4DIMM_SHIFT+i); dimm = 1<<(DCL_x4DIMM_SHIFT+i);
#if K8_4RANK_DIMM_SUPPORT == 1 #if QRANK_DIMM_SUPPORT == 1
if(rank==4) { if(rank==4) {
dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2); dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
} }