board/intel/amenia: Enable LPSS S0ix
This setting will enable S0ix for LPSS Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15056 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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@ -15,6 +15,9 @@ chip soc/intel/apollolake
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# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
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register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
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# LPSS S0ix Enable
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register "lpss_s0ix_enable" = "1"
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device domain 0 on
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device pci 00.0 on end # - Host Bridge
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device pci 00.1 on end # - DPTF
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