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board/intel/amenia: Enable LPSS S0ix 

This setting will enable S0ix for LPSS

Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15056
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Hannah Williams 2016-06-02 15:00:36 -07:00 committed by Martin Roth
parent e1d6aa6e41
commit 7124882aeb
1 changed files with 3 additions and 0 deletions
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src/mainboard/intel/amenia/devicetree.cb
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@ -15,6 +15,9 @@ chip soc/intel/apollolake
# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
# LPSS S0ix Enable
register "lpss_s0ix_enable" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # - Host Bridge device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF device pci 00.1 on end # - DPTF