soc/intel/skylake: Clean up code by using common FAST_SPI module
This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19055 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Barnali Sarkar
Furquan Shaikh
parent
c261c4b426
commit
7146445be9
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@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_FAST_SPI
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select SOC_INTEL_COMMON_BLOCK_GSPI
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select SOC_INTEL_COMMON_BLOCK_ITSS
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select SOC_INTEL_COMMON_BLOCK_LPSS
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@ -15,7 +15,6 @@ bootblock-y += bootblock/i2c.c
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bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += bootblock/smbus.c
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bootblock-y += flash_controller.c
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bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c
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bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
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bootblock-y += gpio.c
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@ -26,7 +25,6 @@ bootblock-y += pmutil.c
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bootblock-y += spi.c
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bootblock-y += tsc_freq.c
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verstage-y += flash_controller.c
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verstage-y += gspi.c
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verstage-y += monotonic_timer.c
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verstage-y += pch.c
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@ -36,7 +34,6 @@ verstage-y += bootblock/i2c.c
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verstage-y += spi.c
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verstage-y += tsc_freq.c
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romstage-y += flash_controller.c
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romstage-y += gpio.c
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romstage-y += gspi.c
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romstage-y += bootblock/i2c.c
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@ -61,7 +58,6 @@ ramstage-y += cpu_info.c
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ramstage-y += dsp.c
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ramstage-y += elog.c
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ramstage-y += finalize.c
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ramstage-y += flash_controller.c
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ramstage-y += gpio.c
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ramstage-y += gspi.c
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ramstage-y += i2c.c
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@ -98,7 +94,6 @@ smm-y += monotonic_timer.c
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smm-y += pch.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c
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smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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smm-y += tsc_freq.c
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smm-$(CONFIG_UART_DEBUG) += uart_debug.c
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@ -14,20 +14,20 @@
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <delay.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/intel/microcode/microcode.c>
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#include <reset.h>
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#include <cpu/x86/mtrr.h>
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#include <delay.h>
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#include <intelblocks/fast_spi.h>
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#include <lib.h>
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#include <reset.h>
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#include <soc/bootblock.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/spi.h>
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#include <stdint.h>
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/* Soft Reset Data Register Bit 12 = MAX Boot Frequency */
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#define SPI_STRAP_MAX_FREQ (1<<12)
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@ -36,14 +36,7 @@
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static void set_pch_cpu_strap(u8 flex_ratio)
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{
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uint8_t *spibar = (void *)SPI_BASE_ADDRESS;
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u32 ssl, ssms, soft_reset_data;
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/* Set Strap Lock Disable */
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ssl = read32(spibar + SPIBAR_RESET_LOCK);
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ssl |= SPIBAR_RESET_LOCK_DISABLE;
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write32(spibar + SPIBAR_RESET_LOCK, ssl);
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u32 soft_reset_data;
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/* Soft Reset Data Register Bit 12 = MAX Boot Frequency
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* Bit 6-11 = Flex Ratio
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@ -51,17 +44,7 @@ static void set_pch_cpu_strap(u8 flex_ratio)
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*/
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soft_reset_data = SPI_STRAP_MAX_FREQ;
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soft_reset_data |= (flex_ratio << FLEX_RATIO_BIT);
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write32(spibar + SPIBAR_RESET_DATA, soft_reset_data);
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/* Set Strap Mux Select set to '1' */
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ssms = read32(spibar + SPIBAR_RESET_CTRL);
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ssms |= SPIBAR_RESET_CTRL_SSMC;
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write32(spibar + SPIBAR_RESET_CTRL, ssms);
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/* Set Strap Lock Enable */
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ssl = read32(spibar + SPIBAR_RESET_LOCK);
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ssl |= SPIBAR_RESET_LOCK_ENABLE;
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write32(spibar + SPIBAR_RESET_LOCK, ssl);
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fast_spi_set_strap_msg_data(soft_reset_data);
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}
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static void set_flex_ratio_to_tdp_nominal(void)
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@ -18,6 +18,7 @@
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#include <chip.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/pcr.h>
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#include <intelblocks/rtc.h>
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@ -46,38 +47,6 @@
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#define PCR_DMI_LPCIOD 0x2770
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#define PCR_DMI_LPCIOE 0x2774
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/*
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* Enable Prefetching and Caching.
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*/
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static void enable_spi_prefetch(void)
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{
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u8 reg8 = pci_read_config8(PCH_DEV_SPI, 0xdc);
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reg8 &= ~(3 << 2);
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reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
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pci_write_config8(PCH_DEV_SPI, 0xdc, reg8);
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}
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static void enable_spibar(void)
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{
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device_t dev = PCH_DEV_SPI;
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u8 pcireg;
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/* Assign Resources to SPI Controller */
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/* Clear BIT 1-2 SPI Command Register */
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pcireg = pci_read_config8(dev, PCI_COMMAND);
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pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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pci_write_config8(dev, PCI_COMMAND, pcireg);
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/* Program Temporary BAR for SPI */
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pci_write_config32(dev, PCI_BASE_ADDRESS_0,
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SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY);
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/* Enable Bus Master and MMIO Space */
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pcireg = pci_read_config8(dev, PCI_COMMAND);
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pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_write_config8(dev, PCI_COMMAND, pcireg);
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}
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static void enable_p2sbbar(void)
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{
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device_t dev = PCH_DEV_P2SB;
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@ -99,8 +68,7 @@ static void enable_p2sbbar(void)
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void bootblock_pch_early_init(void)
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{
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enable_spibar();
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enable_spi_prefetch();
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fast_spi_early_init(SPI_BASE_ADDRESS);
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enable_p2sbbar();
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}
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@ -21,10 +21,10 @@
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#include <console/post_codes.h>
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#include <cpu/x86/smm.h>
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#include <device/pci.h>
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/pcr.h>
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#include <reg_script.h>
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#include <spi-generic.h>
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#include <stdlib.h>
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#include <soc/lpc.h>
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#include <soc/me.h>
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#include <soc/p2sb.h>
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@ -32,8 +32,8 @@
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <soc/smbus.h>
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#include <soc/spi.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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#define PCR_DMI_GCS 0x274C
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#define PCR_DMI_GCS_BILD (1 << 0)
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@ -87,8 +87,7 @@ static void pch_disable_heci(void)
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static void pch_finalize_script(void)
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{
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device_t dev;
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uint32_t reg32, hsfs;
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void *spibar = get_spi_bar();
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uint32_t reg32;
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u16 tcobase;
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u16 tcocnt;
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uint8_t *pmcbase;
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@ -96,15 +95,11 @@ static void pch_finalize_script(void)
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u32 pmsyncreg;
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u8 reg8;
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/* Set SPI opcode menu */
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write16(spibar + SPIBAR_PREOP, SPI_OPPREFIX);
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write16(spibar + SPIBAR_OPTYPE, SPI_OPTYPE);
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write32(spibar + SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER);
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write32(spibar + SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER);
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/* Lock SPIBAR */
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hsfs = read32(spibar + SPIBAR_HSFS);
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hsfs |= SPIBAR_HSFS_FLOCKDN;
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write32(spibar + SPIBAR_HSFS, hsfs);
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/* Set FAST_SPI opcode menu */
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fast_spi_set_opcode_menu();
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/* Lock FAST_SPIBAR */
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fast_spi_lock_bar();
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/*TCO Lock down */
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tcobase = smbus_tco_regs();
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@ -177,12 +172,9 @@ static void soc_lockdown(void)
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BIOS_CNTL) | LPC_BC_BILD);
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/* Reads back for posted write to take effect */
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pci_read_config8(PCH_DEV_LPC, BIOS_CNTL);
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pci_write_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL,
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pci_read_config32(PCH_DEV_SPI,
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SPIBAR_BIOS_CNTL) |
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SPIBAR_BC_BILD);
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/* Reads back for posted write to take effect */
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pci_read_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL);
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fast_spi_set_bios_interface_lock_down();
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/* GCS reg of DMI */
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pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
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}
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@ -192,9 +184,8 @@ static void soc_lockdown(void)
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pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
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pci_read_config8(PCH_DEV_LPC,
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BIOS_CNTL) | LPC_BC_LE);
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pci_write_config8(PCH_DEV_SPI, BIOS_CNTL,
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pci_read_config8(PCH_DEV_SPI,
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BIOS_CNTL) | SPIBAR_BC_LE);
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fast_spi_set_lock_enable();
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}
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/* SPIEiss */
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@ -202,10 +193,8 @@ static void soc_lockdown(void)
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pci_write_config8(PCH_DEV_LPC, BIOS_CNTL,
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pci_read_config8(PCH_DEV_LPC,
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BIOS_CNTL) | LPC_BC_EISS);
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pci_write_config8(PCH_DEV_SPI, BIOS_CNTL,
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pci_read_config8(PCH_DEV_SPI,
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SPIBAR_BIOS_CNTL) |
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SPIBAR_BC_EISS);
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fast_spi_set_eiss();
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}
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}
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@ -1,378 +0,0 @@
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/*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* This file is derived from the flashrom project. */
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#include <arch/early_variables.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <bootstate.h>
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#include <timer.h>
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#include <soc/flash_controller.h>
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#include <soc/intel/common/spi_flash.h>
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#include <soc/pci_devs.h>
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#include <soc/spi.h>
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#include <spi-generic.h>
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static inline uint16_t spi_flash_read_hsfs(pch_spi_flash_regs * const regs)
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{
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return readw_(®s->hsfs);
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}
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static inline void spi_flash_clear_status(pch_spi_flash_regs * const regs)
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{
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/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
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writew_(spi_flash_read_hsfs(regs), ®s->hsfs);
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}
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static inline uint16_t spi_flash_read_hsfc(pch_spi_flash_regs * const regs)
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{
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return readw_(®s->hsfc);
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}
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static inline uint32_t spi_flash_read_faddr(pch_spi_flash_regs * const regs)
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{
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return readl_(®s->faddr) & SPIBAR_FADDR_MASK;
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}
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/*
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* Polls for Cycle Done Status, Flash Cycle Error
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* Resets all error flags in HSFS.
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* Returns 0 if the cycle completes successfully without errors within
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* timeout, 1 on errors.
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*/
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static int wait_for_completion(pch_spi_flash_regs * const regs, int timeout_ms,
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size_t len)
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{
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uint16_t hsfs;
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uint16_t hsfc;
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uint32_t addr;
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struct stopwatch sw;
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int timeout = 0;
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stopwatch_init_msecs_expire(&sw, timeout_ms);
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do {
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hsfs = spi_flash_read_hsfs(regs);
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if ((hsfs & (HSFS_FDONE | HSFS_FCERR)))
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break;
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} while (!(timeout = stopwatch_expired(&sw)));
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if (timeout) {
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addr = spi_flash_read_faddr(regs);
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hsfc = spi_flash_read_hsfc(regs);
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printk(BIOS_ERR, "%ld ms Transaction timeout between offset "
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"0x%08x and 0x%08zx (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n",
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stopwatch_duration_msecs(&sw), addr, addr + len - 1,
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addr, len - 1, hsfc, hsfs);
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return 1;
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}
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if (hsfs & HSFS_FCERR) {
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addr = spi_flash_read_faddr(regs);
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hsfc = spi_flash_read_hsfc(regs);
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printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
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"0x%08zx (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n",
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addr, addr + len - 1, addr, len - 1,
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hsfc, hsfs);
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return 1;
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}
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return 0;
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}
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/* Start operation returning 0 on success, non-zero on error or timeout. */
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static int spi_flash_do_operation(int op, size_t offset, size_t size,
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int timeout_ms)
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{
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uint16_t hsfc;
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pch_spi_flash_regs * const regs = get_spi_bar();
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/* Clear status prior to operation. */
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spi_flash_clear_status(regs);
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/* Set the FADDR */
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writel_(offset & SPIBAR_FADDR_MASK, ®s->faddr);
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hsfc = readw_(®s->hsfc);
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/* Clear then set the correct op. */
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hsfc &= ~HSFC_FCYCLE_MASK;
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hsfc |= op;
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/* Set the size field */
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hsfc &= ~HSFC_FDBC_MASK;
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/* Check for sizes of confirming operations. */
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if (size && size <= SPI_FDATA_BYTES)
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hsfc |= ((size - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC_MASK;
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/* start operation */
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hsfc |= HSFC_FGO;
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writew_(hsfc, ®s->hsfc);
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return wait_for_completion(regs, timeout_ms, size);
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}
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unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
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{
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return min(SPI_FDATA_BYTES, buf_len);
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}
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static size_t spi_get_flash_size(pch_spi_flash_regs *spi_bar)
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{
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uint32_t flcomp;
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size_t size;
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writel_(SPIBAR_FDOC_COMPONENT, &spi_bar->fdoc);
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flcomp = readl_(&spi_bar->fdod);
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switch (flcomp & FLCOMP_C0DEN_MASK) {
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case FLCOMP_C0DEN_8MB:
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size = 8*MiB;
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break;
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case FLCOMP_C0DEN_16MB:
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size = 16*MiB;
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break;
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case FLCOMP_C0DEN_32MB:
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size = 32*MiB;
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break;
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default:
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size = 16*MiB;
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}
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return size;
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}
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|
||||
void spi_flash_init(void)
|
||||
{
|
||||
uint8_t bios_cntl;
|
||||
device_t dev = PCH_DEV_SPI;
|
||||
|
||||
/* Disable the BIOS write protect so write commands are allowed. */
|
||||
pci_read_config_byte(dev, SPIBAR_BIOS_CNTL, &bios_cntl);
|
||||
bios_cntl &= ~SPIBAR_BC_EISS;
|
||||
bios_cntl |= SPIBAR_BC_WPD;
|
||||
pci_write_config_byte(dev, SPIBAR_BIOS_CNTL, bios_cntl);
|
||||
}
|
||||
|
||||
int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len)
|
||||
{
|
||||
u32 start, end, erase_size;
|
||||
int ret = 0;
|
||||
|
||||
erase_size = flash->sector_size;
|
||||
if (offset % erase_size || len % erase_size) {
|
||||
printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
start = offset;
|
||||
end = start + len;
|
||||
|
||||
while (offset < end) {
|
||||
if (spi_flash_do_operation(HSFC_FCYCLE_4KE, offset, 0, 5000)) {
|
||||
printk(BIOS_ERR, "SF: Erase failed at %x\n", offset);
|
||||
ret = -1;
|
||||
goto out;
|
||||
}
|
||||
|
||||
offset += erase_size;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n",
|
||||
len, start);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void pch_read_data(uint8_t *data, int len)
|
||||
{
|
||||
int i;
|
||||
pch_spi_flash_regs *spi_bar;
|
||||
uint32_t temp32 = 0;
|
||||
|
||||
spi_bar = get_spi_bar();
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if ((i % 4) == 0)
|
||||
temp32 = readl_((uint8_t *)spi_bar->fdata + i);
|
||||
|
||||
data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
|
||||
}
|
||||
}
|
||||
|
||||
int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
|
||||
void *buf)
|
||||
{
|
||||
uint8_t block_len;
|
||||
|
||||
if (addr + len > spi_get_flash_size(get_spi_bar())) {
|
||||
printk(BIOS_ERR,
|
||||
"Attempt to read %x-%x which is out of chip\n",
|
||||
(unsigned int) addr,
|
||||
(unsigned int) addr + (unsigned int)len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
while (len > 0) {
|
||||
const int timeout_ms = 6;
|
||||
|
||||
block_len = min(len, SPI_FDATA_BYTES);
|
||||
if (block_len > (~addr & 0xff))
|
||||
block_len = (~addr & 0xff) + 1;
|
||||
|
||||
if (spi_flash_do_operation(HSFC_FCYCLE_RD, addr, block_len,
|
||||
timeout_ms))
|
||||
return -1;
|
||||
|
||||
pch_read_data(buf, block_len);
|
||||
addr += block_len;
|
||||
buf += block_len;
|
||||
len -= block_len;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Fill len bytes from the data array into the fdata/spid registers.
|
||||
*
|
||||
* Note that using len > flash->pgm->spi.max_data_write will trash the registers
|
||||
* following the data registers.
|
||||
*/
|
||||
static void pch_fill_data(const uint8_t *data, int len)
|
||||
{
|
||||
uint32_t temp32 = 0;
|
||||
int i;
|
||||
pch_spi_flash_regs *spi_bar;
|
||||
|
||||
spi_bar = get_spi_bar();
|
||||
if (len <= 0)
|
||||
return;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if ((i % 4) == 0)
|
||||
temp32 = 0;
|
||||
|
||||
temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
|
||||
|
||||
if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
|
||||
writel_(temp32,
|
||||
(uint8_t *)spi_bar->fdata + (i - (i % 4)));
|
||||
}
|
||||
i--;
|
||||
if ((i % 4) != 3) /* Write remaining data to regs. */
|
||||
writel_(temp32, (uint8_t *)spi_bar->fdata + (i - (i % 4)));
|
||||
}
|
||||
|
||||
int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
|
||||
const void *buf)
|
||||
{
|
||||
uint8_t block_len;
|
||||
uint32_t start = addr;
|
||||
pch_spi_flash_regs *spi_bar;
|
||||
|
||||
spi_bar = get_spi_bar();
|
||||
|
||||
if (addr + len > spi_get_flash_size(spi_bar)) {
|
||||
printk(BIOS_ERR,
|
||||
"Attempt to write 0x%x-0x%x which is out of chip\n",
|
||||
(unsigned int)addr, (unsigned int)(addr + len));
|
||||
return -1;
|
||||
}
|
||||
|
||||
while (len > 0) {
|
||||
const int timeout_ms = 6;
|
||||
|
||||
block_len = min(len, sizeof(spi_bar->fdata));
|
||||
if (block_len > (~addr & 0xff))
|
||||
block_len = (~addr & 0xff) + 1;
|
||||
|
||||
pch_fill_data(buf, block_len);
|
||||
if (spi_flash_do_operation(HSFC_FCYCLE_WR, addr, block_len,
|
||||
timeout_ms)) {
|
||||
printk(BIOS_ERR, "SF: write failure at %x\n", addr);
|
||||
return -1;
|
||||
}
|
||||
addr += block_len;
|
||||
buf += block_len;
|
||||
len -= block_len;
|
||||
}
|
||||
printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
|
||||
(unsigned int)(addr - start), start);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg)
|
||||
{
|
||||
size_t block_len = SPI_READ_STATUS_LENGTH;
|
||||
const int timeout_ms = 6;
|
||||
|
||||
if (spi_flash_do_operation(HSFC_FCYCLE_RS, 0, block_len, timeout_ms))
|
||||
return -1;
|
||||
|
||||
pch_read_data(reg, block_len);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct spi_flash boot_flash CAR_GLOBAL;
|
||||
|
||||
struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force)
|
||||
{
|
||||
struct spi_flash *flash;
|
||||
|
||||
flash = car_get_var_ptr(&boot_flash);
|
||||
|
||||
/* Ensure writes can take place to the flash. */
|
||||
spi_flash_init();
|
||||
|
||||
memcpy(&flash->spi, spi, sizeof(*spi));
|
||||
flash->name = "Opaque HW-sequencing";
|
||||
|
||||
flash->internal_write = pch_hwseq_write;
|
||||
flash->internal_erase = pch_hwseq_erase;
|
||||
flash->internal_read = pch_hwseq_read;
|
||||
flash->internal_status = pch_hwseq_read_status;
|
||||
|
||||
/* The hardware sequencing supports 4KiB or 64KiB erase. Use 4KiB. */
|
||||
flash->sector_size = 4*KiB;
|
||||
|
||||
flash->size = spi_get_flash_size(get_spi_bar());
|
||||
|
||||
return flash;
|
||||
}
|
||||
|
||||
int spi_flash_get_fpr_info(struct fpr_info *info)
|
||||
{
|
||||
pch_spi_flash_regs *spi_bar = get_spi_bar();
|
||||
|
||||
if (!spi_bar)
|
||||
return -1;
|
||||
|
||||
info->base = (uintptr_t)&spi_bar->pr[0];
|
||||
info->max = SPI_FPR_MAX;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if ENV_RAMSTAGE
|
||||
/*
|
||||
* spi_flash_init() needs run unconditionally in every boot (including resume)
|
||||
* to allow write protect to be disabled for eventlog and firmware updates.
|
||||
*/
|
||||
static void spi_flash_init_cb(void *unused)
|
||||
{
|
||||
spi_flash_init();
|
||||
}
|
||||
|
||||
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);
|
||||
#endif
|
||||
|
|
@ -24,7 +24,6 @@ void intel_early_me_status(void);
|
|||
void enable_smbus(void);
|
||||
int smbus_read_byte(unsigned int device, unsigned int address);
|
||||
|
||||
int early_spi_read_wpsr(u8 *sr);
|
||||
void mainboard_fill_spd_data(struct pei_data *pei_data);
|
||||
|
||||
#endif /* _SOC_ROMSTAGE_H_ */
|
||||
|
|
|
|||
|
|
@ -23,7 +23,6 @@
|
|||
void mainboard_memory_init_params(FSPM_UPD *mupd);
|
||||
void systemagent_early_init(void);
|
||||
int smbus_read_byte(unsigned int device, unsigned int address);
|
||||
int early_spi_read_wpsr(u8 *sr);
|
||||
/* Board type */
|
||||
enum board_type {
|
||||
BOARD_TYPE_MOBILE = 0,
|
||||
|
|
|
|||
|
|
@ -1,181 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Intel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_FLASH_CONTROLLER__H_
|
||||
#define _SOC_FLASH_CONTROLLER__H_
|
||||
|
||||
#include <rules.h>
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <spi_flash.h>
|
||||
|
||||
int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len);
|
||||
int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
|
||||
const void *buf);
|
||||
int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
|
||||
void *buf);
|
||||
int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg);
|
||||
|
||||
void spi_flash_init(void);
|
||||
|
||||
#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
|
||||
static u8 readb_(const void *addr)
|
||||
{
|
||||
u8 v = read8(addr);
|
||||
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
|
||||
v, ((unsigned int) addr & 0xffff) - 0xf020);
|
||||
return v;
|
||||
}
|
||||
|
||||
static u16 readw_(const void *addr)
|
||||
{
|
||||
u16 v = read16(addr);
|
||||
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
|
||||
v, ((unsigned int) addr & 0xffff) - 0xf020);
|
||||
return v;
|
||||
}
|
||||
|
||||
static u32 readl_(const void *addr)
|
||||
{
|
||||
u32 v = read32(addr);
|
||||
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
|
||||
v, ((unsigned int) addr & 0xffff) - 0xf020);
|
||||
return v;
|
||||
}
|
||||
|
||||
static void writeb_(u8 b, void *addr)
|
||||
{
|
||||
write8(addr, b);
|
||||
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
|
||||
b, ((unsigned int) addr & 0xffff) - 0xf020);
|
||||
}
|
||||
|
||||
static void writew_(u16 b, void *addr)
|
||||
{
|
||||
write16(addr, b);
|
||||
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
|
||||
b, ((unsigned int) addr & 0xffff) - 0xf020);
|
||||
}
|
||||
|
||||
static void writel_(u32 b, void *addr)
|
||||
{
|
||||
write32(addr, b);
|
||||
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
|
||||
b, ((unsigned int) addr & 0xffff) - 0xf020);
|
||||
}
|
||||
|
||||
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
|
||||
|
||||
#define readb_(a) read8(a)
|
||||
#define readw_(a) read16(a)
|
||||
#define readl_(a) read32(a)
|
||||
#define writeb_(val, addr) write8(addr, val)
|
||||
#define writew_(val, addr) write16(addr, val)
|
||||
#define writel_(val, addr) write32(addr, val)
|
||||
|
||||
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
|
||||
|
||||
#if ENV_SMM
|
||||
#define pci_read_config_byte(dev, reg, targ)\
|
||||
(*(targ) = pci_read_config8(dev, reg))
|
||||
#define pci_read_config_word(dev, reg, targ)\
|
||||
(*(targ) = pci_read_config16(dev, reg))
|
||||
#define pci_read_config_dword(dev, reg, targ)\
|
||||
(*(targ) = pci_read_config32(dev, reg))
|
||||
#define pci_write_config_byte(dev, reg, val)\
|
||||
pci_write_config8(dev, reg, val)
|
||||
#define pci_write_config_word(dev, reg, val)\
|
||||
pci_write_config16(dev, reg, val)
|
||||
#define pci_write_config_dword(dev, reg, val)\
|
||||
pci_write_config32(dev, reg, val)
|
||||
#else /* !ENV_SMM */
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#define pci_read_config_byte(dev, reg, targ)\
|
||||
(*(targ) = pci_read_config8(dev, reg))
|
||||
#define pci_read_config_word(dev, reg, targ)\
|
||||
(*(targ) = pci_read_config16(dev, reg))
|
||||
#define pci_read_config_dword(dev, reg, targ)\
|
||||
(*(targ) = pci_read_config32(dev, reg))
|
||||
#define pci_write_config_byte(dev, reg, val)\
|
||||
pci_write_config8(dev, reg, val)
|
||||
#define pci_write_config_word(dev, reg, val)\
|
||||
pci_write_config16(dev, reg, val)
|
||||
#define pci_write_config_dword(dev, reg, val)\
|
||||
pci_write_config32(dev, reg, val)
|
||||
#endif /* ENV_SMM */
|
||||
|
||||
#define HSFC_FCYCLE_MASK (0xf << HSFC_FCYCLE_SHIFT)
|
||||
#define HSFC_FCYCLE_RD (0x0 << HSFC_FCYCLE_SHIFT)
|
||||
#define HSFC_FCYCLE_WR (0x2 << HSFC_FCYCLE_SHIFT)
|
||||
#define HSFC_FCYCLE_4KE (0x3 << HSFC_FCYCLE_SHIFT)
|
||||
#define HSFC_FCYCLE_64KE (0x4 << HSFC_FCYCLE_SHIFT)
|
||||
#define HSFC_FCYCLE_SFDP (0x5 << HSFC_FCYCLE_SHIFT)
|
||||
#define HSFC_FCYCLE_JEDECID (0x6 << HSFC_FCYCLE_SHIFT)
|
||||
#define HSFC_FCYCLE_WS (0x7 << HSFC_FCYCLE_SHIFT)
|
||||
#define HSFC_FCYCLE_RS (0x8 << HSFC_FCYCLE_SHIFT)
|
||||
#define HSFC_FDBC_MASK (0x3f << HSFC_FDBC_SHIFT)
|
||||
|
||||
#define SPI_READ_STATUS_LENGTH 1 /* Read Status Register 1 */
|
||||
|
||||
#define WPSR_MASK_SRP0_BIT 0x80
|
||||
|
||||
#define SPI_FDATA_REGS 16
|
||||
#define SPI_FDATA_BYTES (SPI_FDATA_REGS * sizeof(uint32_t))
|
||||
|
||||
typedef struct pch_spi_flash_regs {
|
||||
uint32_t bfpr;
|
||||
uint16_t hsfs;
|
||||
uint16_t hsfc;
|
||||
uint32_t faddr;
|
||||
uint32_t dlock;
|
||||
uint32_t fdata[SPI_FDATA_REGS];
|
||||
uint32_t frap;
|
||||
uint32_t freg[6];
|
||||
uint32_t _reserved1[6];
|
||||
uint32_t pr[5];
|
||||
uint32_t gpr0;
|
||||
uint32_t _reserved2;
|
||||
uint32_t _reserved3;
|
||||
uint16_t preop;
|
||||
uint16_t optype;
|
||||
uint8_t opmenu[8];
|
||||
uint32_t bbar;
|
||||
uint32_t fdoc;
|
||||
uint32_t fdod;
|
||||
uint8_t _reserved4[8];
|
||||
uint32_t afc;
|
||||
uint32_t lvscc;
|
||||
uint32_t uvscc;
|
||||
uint8_t _reserved5[4];
|
||||
uint32_t fpb;
|
||||
uint8_t _reserved6[28];
|
||||
uint32_t srdl;
|
||||
uint32_t srdc;
|
||||
uint32_t srd;
|
||||
} __attribute__((packed)) pch_spi_flash_regs;
|
||||
|
||||
enum {
|
||||
HSFS_FDONE = 0x0001,
|
||||
HSFS_FCERR = 0x0002,
|
||||
HSFS_FDV = 0x4000,
|
||||
};
|
||||
|
||||
enum {
|
||||
HSFC_FGO = 0x0001,
|
||||
HSFC_FCYCLE_SHIFT = 1,
|
||||
HSFC_FDBC_SHIFT = 8,
|
||||
};
|
||||
#endif /* _SOC_FLASH_CONTROLLER__H_ */
|
||||
|
|
@ -37,7 +37,6 @@
|
|||
|
||||
u8 pch_revision(void);
|
||||
u16 pch_type(void);
|
||||
u32 pch_read_soft_strap(int id);
|
||||
void pch_log_state(void);
|
||||
#if ENV_RAMSTAGE
|
||||
void pch_disable_devfn(device_t dev);
|
||||
|
|
|
|||
|
|
@ -1,126 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_SPI_H_
|
||||
#define _SOC_SPI_H_
|
||||
|
||||
/*
|
||||
* SPI Opcode Menu setup for SPIBAR lockdown
|
||||
* should support most common flash chips.
|
||||
*/
|
||||
#define SPIDVID_OFFSET 0x0
|
||||
|
||||
/* Reigsters within the SPIBAR */
|
||||
#define SPIBAR_SSFC 0xA1
|
||||
|
||||
#define SPIBAR_PREOP 0xA4
|
||||
#define SPIBAR_OPTYPE 0xA6
|
||||
#define SPIBAR_OPMENU_LOWER 0xA8
|
||||
#define SPIBAR_OPMENU_UPPER 0xAc
|
||||
/* STRAP LOCK Register */
|
||||
#define SPIBAR_RESET_LOCK 0xF0
|
||||
#define SPIBAR_RESET_LOCK_DISABLE 0
|
||||
#define SPIBAR_RESET_LOCK_ENABLE 1
|
||||
/* STRAP MSG Control Register*/
|
||||
#define SPIBAR_RESET_CTRL 0xF4
|
||||
#define SPIBAR_RESET_CTRL_SSMC 1
|
||||
/* STRAP Data Register*/
|
||||
#define SPIBAR_RESET_DATA 0xF8
|
||||
|
||||
#define SPI_FPR_MAX 5
|
||||
|
||||
#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
|
||||
#define SPI_OPTYPE_0 0x01 /* Write, no address */
|
||||
|
||||
#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
|
||||
#define SPI_OPTYPE_1 0x03 /* Write, address required */
|
||||
|
||||
#define SPI_OPMENU_2 0x03 /* READ: Read Data */
|
||||
#define SPI_OPTYPE_2 0x02 /* Read, address required */
|
||||
|
||||
#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
|
||||
#define SPI_OPTYPE_3 0x00 /* Read, no address */
|
||||
|
||||
#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
|
||||
#define SPI_OPTYPE_4 0x03 /* Write, address required */
|
||||
|
||||
#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
|
||||
#define SPI_OPTYPE_5 0x00 /* Read, no address */
|
||||
|
||||
#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
|
||||
#define SPI_OPTYPE_6 0x03 /* Write, address required */
|
||||
|
||||
#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
|
||||
#define SPI_OPTYPE_7 0x02 /* Read, address required */
|
||||
|
||||
#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
|
||||
(SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
|
||||
#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
|
||||
(SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
|
||||
|
||||
#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
|
||||
(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
|
||||
(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
|
||||
(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
|
||||
|
||||
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
|
||||
|
||||
#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
|
||||
#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
|
||||
#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
|
||||
#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
|
||||
#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
|
||||
#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
|
||||
#define SPIBAR_HSFS_BERASE_MASK 3 /* Block/Sector Erase MASK */
|
||||
#define SPIBAR_HSFS_BERASE_OFFSET 3 /* Block/Sector Erase OFFSET */
|
||||
#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
|
||||
#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
|
||||
#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
|
||||
#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
|
||||
#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
|
||||
#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
|
||||
#define SPIBAR_FADDR 0x08 /* SPI flash address */
|
||||
#define SPIBAR_FADDR_MASK 0x7FFFFFF
|
||||
|
||||
#define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */
|
||||
#define SPIBAR_FPR(n) (0x84 + (4 * n)) /* SPI flash protected range */
|
||||
#define SPIBAR_FPR_WPE (1 << 31) /* Flash Write protected */
|
||||
#define SPIBAR_SSFS 0xA0
|
||||
#define SPIBAR_SSFS_ERROR (1 << 3)
|
||||
#define SPIBAR_SSFS_DONE (1 << 2)
|
||||
#define SPIBAR_SSFC 0xA1
|
||||
#define SPIBAR_SSFC_DATA (1 << 14)
|
||||
#define SPIBAR_SSFC_GO (1 << 1)
|
||||
|
||||
#define SPIBAR_FDOC 0xB4
|
||||
#define SPIBAR_FDOC_COMPONENT (1 << 12)
|
||||
#define SPIBAR_FDOC_FDSI_1 (1 << 2)
|
||||
|
||||
#define SPIBAR_FDOD 0xB8
|
||||
#define FLCOMP_C0DEN_MASK 0xF
|
||||
#define FLCOMP_C0DEN_8MB 4
|
||||
#define FLCOMP_C0DEN_16MB 5
|
||||
#define FLCOMP_C0DEN_32MB 6
|
||||
|
||||
#define SPIBAR_BIOS_CNTL 0xDC
|
||||
#define SPIBAR_BC_BILD (1 << 7)
|
||||
#define SPIBAR_BC_EISS (1 << 5)
|
||||
#define SPIBAR_BC_LE (1 << 2)
|
||||
#define SPIBAR_BC_WPD (1 << 0)
|
||||
|
||||
void *get_spi_bar(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -15,16 +15,15 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <soc/pch.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/ramstage.h>
|
||||
#include <soc/spi.h>
|
||||
|
||||
u8 pch_revision(void)
|
||||
{
|
||||
|
|
@ -36,34 +35,6 @@ u16 pch_type(void)
|
|||
return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);
|
||||
}
|
||||
|
||||
void *get_spi_bar(void)
|
||||
{
|
||||
device_t dev = PCH_DEV_SPI;
|
||||
uint32_t bar;
|
||||
|
||||
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
/* Bits 31-12 are the base address as per EDS for SPI 1F/5,
|
||||
* Don't care about 0-11 bit
|
||||
*/
|
||||
return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
|
||||
}
|
||||
|
||||
u32 pch_read_soft_strap(int id)
|
||||
{
|
||||
uint32_t fdoc;
|
||||
void *spibar = get_spi_bar();
|
||||
|
||||
fdoc = read32(spibar + SPIBAR_FDOC);
|
||||
fdoc &= ~0x00007ffc;
|
||||
write32(spibar + SPIBAR_FDOC, fdoc);
|
||||
|
||||
fdoc |= 0x00004000;
|
||||
fdoc |= id * 4;
|
||||
write32(spibar + SPIBAR_FDOC, fdoc);
|
||||
|
||||
return read32(spibar + SPIBAR_FDOD);
|
||||
}
|
||||
|
||||
#if ENV_RAMSTAGE
|
||||
void pch_enable_dev(device_t dev)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -5,5 +5,4 @@ romstage-y += pmc.c
|
|||
romstage-y += power_state.c
|
||||
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
|
||||
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
|
||||
romstage-y += spi.c
|
||||
romstage-y += systemagent.c
|
||||
|
|
|
|||
|
|
@ -14,8 +14,6 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/cbfs.h>
|
||||
|
|
@ -30,6 +28,7 @@
|
|||
#include <device/pci.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <elog.h>
|
||||
#include <intelblocks/fast_spi.h>
|
||||
#include <reset.h>
|
||||
#include <romstage_handoff.h>
|
||||
#include <soc/pci_devs.h>
|
||||
|
|
@ -38,8 +37,9 @@
|
|||
#include <soc/pmc.h>
|
||||
#include <soc/serialio.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <soc/spi.h>
|
||||
#include <stage_cache.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <timestamp.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
|
|
@ -58,7 +58,7 @@ int get_sw_write_protect_state(void)
|
|||
u8 status;
|
||||
|
||||
/* Return unprotected status if status read fails. */
|
||||
return early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80);
|
||||
return fast_spi_flash_read_wpsr(&status) ? 0 : !!(status & 0x80);
|
||||
}
|
||||
|
||||
/* UPD parameters to be initialized before MemoryInit */
|
||||
|
|
|
|||
|
|
@ -1,43 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
* Copyright (C) 2015 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/flash_controller.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <spi-generic.h>
|
||||
|
||||
/*
|
||||
* Minimal set of commands to read WPSR from SPI.
|
||||
* Returns 0 on success, < 0 on failure.
|
||||
*/
|
||||
int early_spi_read_wpsr(u8 *sr)
|
||||
{
|
||||
uint8_t rdsr;
|
||||
int ret = 0;
|
||||
|
||||
spi_flash_init();
|
||||
|
||||
/* sending NULL for spiflash struct parameter since we are not
|
||||
* calling HWSEQ read_status() call via Probe.
|
||||
*/
|
||||
ret = pch_hwseq_read_status(NULL, &rdsr);
|
||||
if (ret) {
|
||||
printk(BIOS_ERR, "SPI rdsr failed\n");
|
||||
return ret;
|
||||
}
|
||||
*sr = rdsr & WPSR_MASK_SRP0_BIT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -15,8 +15,6 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <delay.h>
|
||||
#include <types.h>
|
||||
#include <arch/hlt.h>
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
|
|
@ -24,10 +22,13 @@
|
|||
#include <cpu/x86/smm.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <elog.h>
|
||||
#include <intelblocks/fast_spi.h>
|
||||
#include <intelblocks/pcr.h>
|
||||
#include <delay.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <elog.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <spi-generic.h>
|
||||
#include <soc/flash_controller.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/lpc.h>
|
||||
#include <soc/nvs.h>
|
||||
|
|
@ -37,6 +38,7 @@
|
|||
#include <soc/pm.h>
|
||||
#include <soc/pmc.h>
|
||||
#include <soc/smm.h>
|
||||
#include <types.h>
|
||||
|
||||
/* IO Trap PCRs */
|
||||
/* Trap status Register */
|
||||
|
|
@ -286,7 +288,7 @@ static void finalize(void)
|
|||
|
||||
if (IS_ENABLED(CONFIG_SPI_FLASH_SMM))
|
||||
/* Re-init SPI driver to handle locked BAR */
|
||||
spi_flash_init();
|
||||
fast_spi_init();
|
||||
}
|
||||
|
||||
static void southbridge_smi_apmc(void)
|
||||
|
|
|
|||
Loading…
Reference in New Issue