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AMD fam10 ACPI: Use common fixed sleepstates.asl 

SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.

Note that all boards incorrectly had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.

Change-Id: Ia948becff079383cbf861468da9e8a3ebbf213cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
Kyösti Mälkki 2017-08-07 20:10:28 +03:00
parent 390ba044dc
commit 714709fde6
25 changed files with 23 additions and 530 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/mainboard/advansus/a785e-i/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -796,27 +794,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/amd/bimini_fam10/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -796,27 +794,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/amd/dbm690t/dsdt.asl
View File

@ -36,8 +36,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -763,27 +761,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/amd/mahogany/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -759,27 +757,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/amd/mahogany_fam10/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/amd/pistachio/dsdt.asl
View File

@ -36,8 +36,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -763,27 +761,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/amd/tilapia_fam10/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/asrock/939a785gmh/dsdt.asl
View File

@ -28,8 +28,6 @@ DefinitionBlock (
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
Name(PMOD, One) /* Assume APIC */ Name(PMOD, One) /* Assume APIC */
/* PIC IRQ mapping registers, C00h-C01h */ /* PIC IRQ mapping registers, C00h-C01h */
@ -428,27 +426,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */

7
src/mainboard/asus/kcma-d8/dsdt.asl
View File

@ -50,13 +50,6 @@ DefinitionBlock (
/* HPET enable */ /* HPET enable */
Name (HPTE, 0x1) Name (HPTE, 0x1)
/* Define power states */
Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */
Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 }) /* Standby */
Name (\_S3, Package () { 0x03, 0x03, 0x00, 0x00 }) /* Suspend to RAM */
Name (\_S4, Package () { 0x04, 0x04, 0x00, 0x00 }) /* Suspend to disk */
Name (\_S5, Package () { 0x05, 0x05, 0x00, 0x00 }) /* Hard power off */
/* The _PIC method is called by the OS to choose between interrupt /* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC. * routing via the i8259 interrupt controller or the APIC.
* *

7
src/mainboard/asus/kgpe-d16/dsdt.asl
View File

@ -50,13 +50,6 @@ DefinitionBlock (
/* HPET enable */ /* HPET enable */
Name (HPTE, 0x1) Name (HPTE, 0x1)
/* Define power states */
Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */
Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 }) /* Standby */
Name (\_S3, Package () { 0x03, 0x03, 0x00, 0x00 }) /* Suspend to RAM */
Name (\_S4, Package () { 0x04, 0x04, 0x00, 0x00 }) /* Suspend to disk */
Name (\_S5, Package () { 0x05, 0x05, 0x00, 0x00 }) /* Hard power off */
/* The _PIC method is called by the OS to choose between interrupt /* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC. * routing via the i8259 interrupt controller or the APIC.
* *

24
src/mainboard/asus/m4a78-em/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/asus/m4a785-m/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/asus/m4a785t-m/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA,CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA,CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/asus/m5a88-v/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -796,27 +794,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/avalue/eax-785e/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -796,27 +794,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/gigabyte/ma785gm/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/gigabyte/ma785gmt/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/gigabyte/ma78gm/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/iei/kino-780am2-fam10/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/jetway/pa78vm5/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -801,27 +799,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/kontron/kt690/dsdt.asl
View File

@ -36,8 +36,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -763,27 +761,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

11
src/mainboard/siemens/sitemp_g1p1/acpi/event.asl
View File

@ -15,16 +15,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
/* Supported sleep states: */ #include <southbridge/amd/common/acpi/sleepstates.asl>
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, ... , S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/supermicro/h8scm_fam10/dsdt.asl
View File

@ -35,8 +35,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -819,27 +817,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/technexion/tim5690/dsdt.asl
View File

@ -36,8 +36,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -763,27 +761,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})

24
src/mainboard/technexion/tim8690/dsdt.asl
View File

@ -36,8 +36,6 @@ DefinitionBlock (
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)
Name(UOM1, 2) Name(UOM1, 2)
@ -763,27 +761,7 @@ DefinitionBlock (
} /* End Scope(_SB) */ } /* End Scope(_SB) */
#include <southbridge/amd/common/acpi/sleepstates.asl>
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
If (LAnd(SSFG, 0x01)) {
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
}
If (LAnd(SSFG, 0x02)) {
Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
}
If (LAnd(SSFG, 0x04)) {
Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
}
If (LAnd(SSFG, 0x08)) {
Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
}
Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
Name(CSMS, 0) /* Current System State */
/* Wake status package */ /* Wake status package */
Name(WKST,Package(){Zero, Zero}) Name(WKST,Package(){Zero, Zero})