Load an IDT with NULL limit

Load an IDT with NULL limit to prevent the 16bit IDT being used
in protected mode before c_start.S sets up a 32bit IDT when entering
ram stage.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I8d048c894c863ac4971fcef8f065be6b899e1d3e
Reviewed-on: http://review.coreboot.org/259
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

src/cpu/x86/16bit/entry16.inc

@@ -45,7 +45,6 @@ _start:
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
 
-
 	/* Invalidating the cache here seems to be a bad idea on
 	 * modern processors.  Don't.
 	 * If we are hyperthreaded or we have multiple cores it is bad,
@@ -55,6 +54,13 @@ _start:
 	 * entry16.inc.
 	 */
 
+	/* Load an IDT with NULL limit to prevent the 16bit IDT being used
+	 * in protected mode before c_start.S sets up a 32bit IDT when entering
+	 * ram stage.
+	 */
+	movw $nullidt_offset, %bx
+	lidt %cs:(%bx)
+
 	/* Note: gas handles memory addresses in 16 bit code very poorly.
 	 * In particular it doesn't appear to have a directive allowing you
 	 * associate a section or even an absolute offset with a segment register.
@@ -118,6 +124,13 @@ gdtptr16:
 	.word	gdt_end - gdt -1 /* compute the table limit */
 	.long	gdt		 /* we know the offset */
 
+.align	4
+.globl nullidt
+nullidt:
+	.word	0	/* limit */
+	.long	0
+	.word	0
+
 .globl _estart
 _estart:
 	.code32

src/cpu/x86/16bit/entry16.lds

@@ -1 +1,2 @@
 	gdtptr16_offset = gdtptr16 & 0xffff;
+	nullidt_offset = nullidt & 0xffff;