rambi: Enable USB boot with EHCI controller
This adds the EHCI driver back to libpayload and configures the devicetree to route ports to EHCI. This is hopefully just temporary until the issues with XHCI can be worked out. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot from USB on rambi Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175513 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4931 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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@ -5,6 +5,24 @@ chip soc/intel/baytrail
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register "sata_ahci" = "0x1"
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register "sata_ahci" = "0x1"
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register "ide_legacy_combined" = "0x0"
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register "ide_legacy_combined" = "0x0"
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# Route USB ports to XHCI -- DISABLED UNTIL XHCI WORKS
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register "usb_route_to_xhci" = "0"
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# USB Port Disable Mask
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register "usb2_port_disable_mask" = "0x0"
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register "usb3_port_disable_mask" = "0x0"
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# USB PHY settings
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# TODO: These values are from Baytrail and need tuned for Rambi board
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register "usb2_per_port_lane0" = "0x00049a09"
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register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
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register "usb2_per_port_lane1" = "0x00049a09"
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register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
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register "usb2_per_port_lane2" = "0x00049209"
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register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
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register "usb2_per_port_lane3" = "0x00049a09"
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register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
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device cpu_cluster 0 on
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device cpu_cluster 0 on
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device lapic 0 on end
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device lapic 0 on end
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end
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end
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