amd/stoneyridge: Add more SMM definitions
Change-Id: I4c8069a18ea430ec6e66d41879c8e77f1ef2b340 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Marshall Dawson
Martin Roth
parent
abac64d4d0
commit
714c087788
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@ -1,8 +1,18 @@
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/*
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* Utilities for SMI handlers and SMM setup
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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* Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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* Subject to the GNU GPL v2, or (at your option) any later version.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__
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@ -10,17 +20,170 @@
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#include <arch/io.h>
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/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it.
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* This is defined by AGESA, but we dpn't include AGESA headers to avoid
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* polluting the namesace.
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*/
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#define SMI_BASE 0xfed80200
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/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it. */
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#define SMI_BASE 0xfed80200
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#define SMI_REG_SMITRIG0 0x98
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#define SMITRG0_EOS (1 << 28)
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#define SMITRG0_SMIENB (1 << 31)
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#define SMI_SCI_STATUS 0x10
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#define SMI_REG_CONTROL0 0xa0
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/* SMI source and status */
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#define SMITYPE_AGPIO65 0
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#define SMITYPE_AGPIO66 1
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#define SMITYPE_AGPIO3 2
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#define SMITYPE_LPCPME_AGPIO22 3
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#define SMITYPE_GPIO4 4
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#define SMITYPE_LPCPD_AGPIOG21 5
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#define SMITYPE_IRTX1_G15 6
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#define SMITYPE_AGPIO5_DEVSLP0 7
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#define SMITYPE_WAKE_AGPIO2 8
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#define SMITYPE_APIO68_SGPIOCLK 9
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#define SMITYPE_AGPIO6 10
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#define SMITYPE_GPIO7 11
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#define SMITYPE_USBOC0_TRST_AGPIO16 12
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#define SMITYPE_USB0C1_TDI_AGPIO17 13
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#define SMITYPE_USBOC2_TCK_AGPIO18 14
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#define SMITYPE_TDO_USB0C3_AGPIO24 15
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#define SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23 16
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/* 17 Reserved */
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#define SMITYPE_BLINK_AGPIO11_USBOC7 18
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#define SMITYPE_SYSRESET_AGPIO1 19
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#define SMITYPE_IRRX1_AGPIO15 20
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#define SMITYPE_IRTX0_USBOC5_AGPIO13 21
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#define SMITYPE_GPIO9_SERPORTRX 22
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#define SMITYPE_GPIO8_SEPORTTX 23
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#define GEVENT_MASK ((1 << SMITYPE_AGPIO65) \
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| (1 << SMITYPE_AGPIO66) \
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| (1 << SMITYPE_AGPIO3) \
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| (1 << SMITYPE_LPCPME_AGPIO22) \
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| (1 << SMITYPE_GPIO4) \
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| (1 << SMITYPE_LPCPD_AGPIOG21) \
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| (1 << SMITYPE_IRTX1_G15) \
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| (1 << SMITYPE_AGPIO5_DEVSLP0) \
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| (1 << SMITYPE_WAKE_AGPIO2) \
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| (1 << SMITYPE_APIO68_SGPIOCLK) \
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| (1 << SMITYPE_AGPIO6) \
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| (1 << SMITYPE_GPIO7) \
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| (1 << SMITYPE_USBOC0_TRST_AGPIO16) \
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| (1 << SMITYPE_USB0C1_TDI_AGPIO17) \
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| (1 << SMITYPE_USBOC2_TCK_AGPIO18) \
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| (1 << SMITYPE_TDO_USB0C3_AGPIO24) \
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| (1 << SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23) \
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| (1 << SMITYPE_BLINK_AGPIO11_USBOC7) \
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| (1 << SMITYPE_SYSRESET_AGPIO1) \
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| (1 << SMITYPE_IRRX1_AGPIO15) \
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| (1 << SMITYPE_IRTX0_USBOC5_AGPIO13) \
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| (1 << SMITYPE_GPIO9_SERPORTRX))
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#define SMITYPE_EHCI0_WAKE 24
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#define SMITYPE_EHCI1_WAKE 25
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#define SMITYPE_ESPI_SYS 26
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#define SMITYPE_ESPI_WAKE_PME 27
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/* 28-32 Reserved */
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#define SMITYPE_FCH_FAKE0 33
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#define SMITYPE_FCH_FAKE1 34
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#define SMITYPE_FCH_FAKE2 35
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/* 36 Reserved */
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#define SMITYPE_SATA_GEVENT0 37
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#define SMITYPE_SATA_GEVENT1 38
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#define SMITYPE_ACP_WAKE 39
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#define SMITYPE_ECG 40
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#define SMITYPE_GPIO_CTL 41
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#define SMITYPE_CIR_PME 42
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#define SMITYPE_ALT_HPET_ALARM 43
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#define SMITYPE_FAN_THERMAL 44
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#define SMITYPE_ASF_MASTER_SLAVE 45
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#define SMITYPE_I2S_WAKE 46
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#define SMITYPE_SMBUS0_MASTER 47
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#define SMITYPE_TWARN 48
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#define SMITYPE_TRAFFIC_MON 49
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#define SMITYPE_ILLB 50
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#define SMITYPE_PWRBUTTON_UP 51
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#define SMITYPE_PROCHOT 52
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#define SMITYPE_APU_HW 53
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#define SMITYPE_NB_SCI 54
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#define SMITYPE_RAS_SERR 55
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#define SMITYPE_XHC0_PME 56
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/* 57 Reserved */
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#define SMITYPE_ACDC_TIMER 58
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/* 59-62 Reserved */
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#define SMITYPE_TEMP_TSI 63
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#define SMITYPE_KB_RESET 64
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#define SMITYPE_SLP_TYP 65
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#define SMITYPE_AL2H_ACPI 66
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#define SMITYPE_AHCI 67
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/* 68-71 Reserved */
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#define SMITYPE_GBL_RLS 72
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#define SMITYPE_BIOS_RLS 73
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#define SMITYPE_PWRBUTTON_DOWN 74
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#define SMITYPE_SMI_CMD_PORT 75
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#define SMITYPE_USB_SMI 76
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#define SMITYPE_SERIRQ 77
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#define SMITYPE_SMBUS0_INTR 78
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#define SMITYPE_IMC 79
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#define SMITYPE_XHC_ERROR 80
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#define SMITYPE_INTRUDER 81
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#define SMITYPE_VBAT_LOW 82
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#define SMITYPE_PROTHOT 83
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#define SMITYPE_PCI_SERR 84
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#define SMITYPE_GPP_SERR 85
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/* 85-88 Reserved */
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#define SMITYPE_TMERTRIP 89
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#define SMITYPE_EMUL60_64 90
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#define SMITYPE_USB_FLR 91
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#define SMITYPE_SATA_FLR 92
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#define SMITYPE_AZ_FLR 93
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/* 94-132 Reserved */
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#define SMITYPE_FANIN0 133
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/* 134-137 Reserved */
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#define SMITYPE_FAKE0 138
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#define SMITYPE_FAKE1 139
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#define SMITYPE_FAKE2 140
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/* 141 Reserved */
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#define SMITYPE_SHORT_TIMER 142
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#define SMITYPE_LONG_TIMER 143
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#define SMITYPE_AB_SMI 144
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#define SMITYPE_SOFT_RESET 145
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/* 146-147 Reserved */
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#define SMITYPE_IOTRAP0 148
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/* 149-151 Reserved */
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#define SMITYPE_MEMTRAP0 152
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/* 153-155 Reserved */
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#define SMITYPE_CFGTRAP0 156
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/* 157-159 Reserved */
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#define NUMBER_SMITYPES 160
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#define TYPE_TO_MASK(X) (1 << (X) % 32)
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#define SMI_REG_SMISTS0 0x80
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#define SMI_REG_SMISTS1 0x84
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#define SMI_REG_SMISTS2 0x88
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#define SMI_REG_SMISTS3 0x8c
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#define SMI_REG_SMISTS4 0x90
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#define SMI_REG_POINTER 0x94
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# define SMI_STATUS_SRC_SCI (1 << 0)
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# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */
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# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */
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# define SMI_STATUS_SRC_2 (1 << 3)
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# define SMI_STATUS_SRC_3 (1 << 4)
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# define SMI_STATUS_SRC_4 (1 << 5)
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#define SMI_TIMER 0x96
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#define SMI_TIMER_MASK 0x7fff
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#define SMI_TIMER_EN (1 << 15)
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#define SMI_REG_SMITRIG0 0x98
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# define SMITRG0_EOS (1 << 28)
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# define SMI_TIMER_SEL (1 << 29)
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# define SMITRG0_SMIENB (1 << 31)
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#define SMI_REG_CONTROL0 0xa0
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#define SMI_REG_CONTROL1 0xa4
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#define SMI_REG_CONTROL2 0xa8
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#define SMI_REG_CONTROL3 0xac
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#define SMI_REG_CONTROL4 0xb0
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#define SMI_REG_CONTROL5 0xb4
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#define SMI_REG_CONTROL6 0xb8
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#define SMI_REG_CONTROL7 0xbc
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#define SMI_REG_CONTROL8 0xc0
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#define SMI_REG_CONTROL9 0xc4
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enum smi_mode {
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SMI_MODE_DISABLE = 0,
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