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sb/intel/lynxpoint/lpc.c: Relocate lock bit write 

This lock bit can be set later, and should also be set for LynxPoint-H.
This eases merging with Broadwell, which already sets this lock bit
after `spi_finalize_ops()` in a dedicated finalisation function.

Tested on Asrock B85M Pro4 (LynxPoint-H), the lock bit is now set.

Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-30 16:26:28 +01:00 committed by Patrick Georgi
parent bd78c5a649
commit 71505f5f47
1 changed files with 3 additions and 3 deletions
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6
src/southbridge/intel/lynxpoint/lpc.c
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@ -485,9 +485,6 @@ static void lpt_lp_pm_init(struct device *dev)
if (RCBA32(FD) & PCH_DISABLE_ADSPD) if (RCBA32(FD) & PCH_DISABLE_ADSPD)
RCBA32_OR(0x2b1c, (1 << 29)); RCBA32_OR(0x2b1c, (1 << 29));
/* Lock */
RCBA32_OR(0x3a6c, 0x00000001);
/* Set RCBA 0x33D4 after other setup */ /* Set RCBA 0x33D4 after other setup */
RCBA32_OR(0x33d4, 0x2fff2fb1); RCBA32_OR(0x33d4, 0x2fff2fb1);
@ -809,6 +806,9 @@ static void lpc_final(struct device *dev)
{ {
spi_finalize_ops(); spi_finalize_ops();
/* Lock */
RCBA32_OR(0x3a6c, 0x00000001);
if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN)) if (acpi_is_wakeup_s3() || CONFIG(INTEL_CHIPSET_LOCKDOWN))
apm_control(APM_CNT_FINALIZE); apm_control(APM_CNT_FINALIZE);
} }