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northbridge/i945/gma: fix build error with native graphics init 

Tested on an X60, Native graphics init still works perfectly.

Change-Id: I91be3baa658e0332028c512c5a4cb0aee07d540a
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/8696
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Francis Rowe 2015-03-16 05:31:40 +00:00 committed by Alexandru Gagniuc
parent ac490b8a6b
commit 71512b2cf6
1 changed files with 8 additions and 10 deletions
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16
src/northbridge/intel/i945/gma.c
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@ -51,7 +51,7 @@
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
static int gtt_setup(unsigned int mmiobase) static int gtt_setup(void *mmiobase)
{ {
unsigned long PGETBL_save; unsigned long PGETBL_save;
unsigned long tom; // top of memory unsigned long tom; // top of memory
@ -87,7 +87,7 @@ static int gtt_setup(unsigned int mmiobase)
static int intel_gma_init(struct northbridge_intel_i945_config *conf, static int intel_gma_init(struct northbridge_intel_i945_config *conf,
unsigned int pphysbase, unsigned int piobase, unsigned int pphysbase, unsigned int piobase,
unsigned int pmmio, unsigned int pgfx) void *pmmio, unsigned int pgfx)
{ {
struct edid edid; struct edid edid;
u8 edid_data[128]; u8 edid_data[128];
@ -107,7 +107,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
u16 reg16; u16 reg16;
printk(BIOS_SPEW, printk(BIOS_SPEW,
"i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n", "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n",
(void *)pgfx, pmmio, piobase, pphysbase); (void *)pgfx, pmmio, piobase, pphysbase);
intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128); intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128);
@ -432,11 +432,12 @@ static void gma_func0_init(struct device *dev)
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
/* This should probably run before post VBIOS init. */ /* This should probably run before post VBIOS init. */
printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
u32 iobase, mmiobase, graphics_base; void *mmiobase;
u32 iobase, graphics_base;
struct northbridge_intel_i945_config *conf = dev->chip_info; struct northbridge_intel_i945_config *conf = dev->chip_info;
iobase = dev->resource_list[1].base; iobase = dev->resource_list[1].base;
mmiobase = dev->resource_list[0].base; mmiobase = (void *)(uintptr_t)dev->resource_list[0].base;
graphics_base = dev->resource_list[2].base; graphics_base = dev->resource_list[2].base;
printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n",
@ -471,16 +472,13 @@ static void gma_func0_disable(struct device *dev)
static void gma_func1_init(struct device *dev) static void gma_func1_init(struct device *dev)
{ {
u32 reg32; u32 reg32;
u8 val;
/* IGD needs to be Bus Master, also enable IO accesss */ /* IGD needs to be Bus Master, also enable IO accesss */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | pci_write_config32(dev, PCI_COMMAND, reg32 |
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
if (get_option(&val, "tft_brightness") == CB_SUCCESS) /* Permanently set tft_brightness to 0xff. Ignore nvramtool configuration */
pci_write_config8(dev, 0xf4, val);
else
pci_write_config8(dev, 0xf4, 0xff); pci_write_config8(dev, 0xf4, 0xff);
} }