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mb/google/poppy/variants/nami: Enable FP MCU 

Some variants of nami will have a fingerprint MCU.

BUG=b:118503113
BRANCH=Nami
TEST=None (build and boot, but no hw yet)

Change-Id: I446dc09cdf7f84a801723cb403d2de80e0997c65
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Shelley Chen 2018-10-26 14:07:16 -07:00 committed by Patrick Georgi
parent 0f14df46aa
commit 715cb40963
3 changed files with 54 additions and 2 deletions
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14
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -277,7 +277,7 @@ chip soc/intel/skylake
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexSpi0] = PchSerialIoPci,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexSpi1] = PchSerialIoPci,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
@ -449,7 +449,17 @@ chip soc/intel/skylake
device spi 0 on end
end
end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1e.3 on
chip drivers/spi/acpi
register "name" = ""CRFP""
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D6_IRQ)"
register "wake" = "GPE0_DW1_06" # GPP_D6
device spi 0 on end
end # FPMCU
end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO
device pci 1e.6 off end # SDCard

34
src/mainboard/google/poppy/variants/nami/gpio.c
View File

@ -408,6 +408,29 @@ static const struct pad_config pantheon_gpio_table[] = {
PAD_CFG_NC(GPP_C3),
};
static const struct pad_config fpmcu_gpio_table[] = {
/* B11 : EXT_PWR_GATE# ==> PCH_FP_PWR_EN */
PAD_CFG_GPO(GPP_B11, 1, DEEP),
/* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS# */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
/* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */
PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
/* B21 : GSPI1_MISO ==> PCH_SPI_FP_MISO */
PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
/* B22 : GSPI1_MOSI ==> PCH_SPI_FP_MOSI */
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
/* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */
PAD_CFG_GPO(GPP_C3, 0, DEEP),
/* C9 : UART0_TXD ==> FP_RST_ODL */
PAD_CFG_GPO(GPP_C9, 1, DEEP),
/* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */
PAD_CFG_GPO(GPP_D5, 0, DEEP),
/* D6 : ISH_I2C0_SCL ==> FPMCU_INT_L */
PAD_CFG_GPI_IRQ_WAKE(GPP_D6, 20K_PU, DEEP, LEVEL, NONE),
/* D17 : DMIC_CLK1 ==> NC */
PAD_CFG_NC(GPP_D17),
};
const struct pad_config *variant_sku_gpio_table(size_t *num)
{
uint32_t sku_id = variant_board_sku();
@ -431,6 +454,17 @@ const struct pad_config *variant_sku_gpio_table(size_t *num)
*num = ARRAY_SIZE(pantheon_gpio_table);
board_gpio_tables = pantheon_gpio_table;
break;
case SKU_0_EKKO:
case SKU_1_EKKO:
case SKU_2_EKKO:
case SKU_3_EKKO:
case SKU_0_BARD:
case SKU_1_BARD:
case SKU_2_BARD:
case SKU_3_BARD:
*num = ARRAY_SIZE(fpmcu_gpio_table);
board_gpio_tables = fpmcu_gpio_table;
break;
default:
*num = ARRAY_SIZE(nami_default_sku_gpio_table);
board_gpio_tables = nami_default_sku_gpio_table;

8
src/mainboard/google/poppy/variants/nami/include/variant/sku.h
View File

@ -34,5 +34,13 @@
#define SKU_1_SYNDRA 0x2BC62
#define SKU_2_SYNDRA 0x2BC61
#define SKU_3_SYNDRA 0X2BC60
#define SKU_0_EKKO 0x118E3
#define SKU_1_EKKO 0x18E3
#define SKU_2_EKKO 0x118E1
#define SKU_3_EKKO 0X18E1
#define SKU_0_BARD 0x19CE3
#define SKU_1_BARD 0x9CE3
#define SKU_2_BARD 0x19CE1
#define SKU_3_BARD 0X9CE1
#endif /* __MAINBOARD_SKU_H__ */