soc/mediatek/mt8192: devapc: Add ADSP domain setting
Configure ADSP domain from 0 to 4 and lock it to prevent changing it unexpectedly. TEST=emerge-asurada coreboot BRANCH=asurada Change-Id: Ib938ba05e8d0342572c57366c97ebb0185da8aba Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52728 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -71,9 +71,10 @@ static void fmem_master_init(uintptr_t base)
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static void scp_master_init(uintptr_t base)
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{
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write32(getreg(base, SCP_DOM), MAS_DOMAIN_3);
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write32(getreg(base, ADSP_DOM), MAS_DOMAIN_4);
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/* Let SCP_DOM register be read-only for security */
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write32(getreg(base, ONETIME_LOCK), 0x1);
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/* Let SCP_DOM and ADSP_DOM registers be read-only for security */
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write32(getreg(base, ONETIME_LOCK), 0x5);
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}
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struct devapc_init {
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@ -23,6 +23,7 @@ enum devapc_ao_offset {
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enum scp_offset {
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SCP_DOM = 0xA5080,
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ADSP_DOM = 0xA5088,
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ONETIME_LOCK = 0xA5104,
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};
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