soc/mediatek/mt8192: devapc: Add ADSP domain setting

Configure ADSP domain from 0 to 4 and lock it to prevent
changing it unexpectedly.

TEST=emerge-asurada coreboot
BRANCH=asurada

Change-Id: Ib938ba05e8d0342572c57366c97ebb0185da8aba
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52728
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tinghan Shen 2021-04-27 17:10:28 +08:00 committed by Patrick Georgi
parent 8ac6e09a10
commit 715cdc370c
2 changed files with 4 additions and 2 deletions

View File

@ -71,9 +71,10 @@ static void fmem_master_init(uintptr_t base)
static void scp_master_init(uintptr_t base) static void scp_master_init(uintptr_t base)
{ {
write32(getreg(base, SCP_DOM), MAS_DOMAIN_3); write32(getreg(base, SCP_DOM), MAS_DOMAIN_3);
write32(getreg(base, ADSP_DOM), MAS_DOMAIN_4);
/* Let SCP_DOM register be read-only for security */ /* Let SCP_DOM and ADSP_DOM registers be read-only for security */
write32(getreg(base, ONETIME_LOCK), 0x1); write32(getreg(base, ONETIME_LOCK), 0x5);
} }
struct devapc_init { struct devapc_init {

View File

@ -23,6 +23,7 @@ enum devapc_ao_offset {
enum scp_offset { enum scp_offset {
SCP_DOM = 0xA5080, SCP_DOM = 0xA5080,
ADSP_DOM = 0xA5088,
ONETIME_LOCK = 0xA5104, ONETIME_LOCK = 0xA5104,
}; };