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soc/intel/*: drop broken LPC mmio code 

The code for setting the LPC generic memory range uses an array of fixed
address ranges not needing explicit decoding, to decide if the address
needs to be written to the LGMR register. Most platforms only mistakenly
add the PCH reserved mmio range, that is not decoded generally,
effectively breaking the mechanism. Only APL uses the array correctly.

That code, in it's current state, does not work (except for APL) and
currently, there is not a single user. Thus, drop it before people start
using it.

Change-Id: I723415fedd1b1d95c502badf7b0510a1338b11ac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner 2021-01-17 01:42:15 +01:00
parent 2cbe3df2cd
commit 71624cd94f
12 changed files with 0 additions and 170 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/soc/intel/alderlake/espi.c
View File

@ -20,21 +20,6 @@
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
/*
* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
* certain memory range as reserved range for BIOS usage.
* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
*/
static const struct lpc_mmio_range lpc_fixed_mmio_ranges[] = {
{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
{ 0, 0 }
};
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
{
return lpc_fixed_mmio_ranges;
}
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();

19
src/soc/intel/apollolake/lpc.c
View File

@ -8,25 +8,6 @@
#include <soc/pm.h>
#include "chip.h"
static const struct lpc_mmio_range apl_lpc_fixed_mmio_ranges[] = {
{ 0xfed40000, 0x8000 },
{ 0xfedc0000, 0x4000 },
{ 0xfed20800, 16 },
{ 0xfed20880, 8 },
{ 0xfed208e0, 16 },
{ 0xfed208f0, 8 },
{ 0xfed30800, 16 },
{ 0xfed30880, 8 },
{ 0xfed308e0, 16 },
{ 0xfed308f0, 8 },
{ 0, 0 }
};
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
{
return apl_lpc_fixed_mmio_ranges;
}
static const struct pad_config lpc_gpios[] = {
#if CONFIG(SOC_INTEL_GEMINILAKE)
#if !CONFIG(SOC_ESPI)

15
src/soc/intel/cannonlake/lpc.c
View File

@ -18,21 +18,6 @@
#include "chip.h"
/*
* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
* certain memory range as reserved range for BIOS usage.
* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
*/
static const struct lpc_mmio_range cnl_lpc_fixed_mmio_ranges[] = {
{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
{ 0, 0 }
};
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
{
return cnl_lpc_fixed_mmio_ranges;
}
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();

9
src/soc/intel/common/block/include/intelblocks/lpc_lib.h
View File

@ -45,11 +45,6 @@ enum serirq_mode {
SERIRQ_OFF,
};
struct lpc_mmio_range {
uintptr_t base;
size_t size;
};
/*
* Enable fixed IO ranges to LPC. IOE_* macros can be OR'ed together.
* Output:I/O Enable Bits
@ -65,8 +60,6 @@ void lpc_open_pmio_window(uint16_t base, uint16_t size);
void lpc_close_pmio_windows(void);
/* Open a generic MMIO window to the LPC bus. One window is available. */
void lpc_open_mmio_window(uintptr_t base, size_t size);
/* Returns true if given window is decoded to LPC via a fixed range. */
bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size);
/* Init SoC Specific LPC features. Common definition will be weak and
each soc will need to define the init. */
void lpc_soc_init(struct device *dev);
@ -74,8 +67,6 @@ void lpc_soc_init(struct device *dev);
void pch_lpc_soc_fill_io_resources(struct device *dev);
/* Init LPC GPIO pads */
void lpc_configure_pads(void);
/* Get SoC specific MMIO ranges */
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void);
/* Set LPC BIOS Control BILD bit. */
void lpc_set_bios_interface_lock_down(void);
/* Set LPC BIOS Control LE bit. */

8
src/soc/intel/common/block/lpc/lpc.c
View File

@ -59,14 +59,6 @@ static void pch_lpc_loop_resources(struct device *dev)
for (res = dev->resource_list; res; res = res->next) {
if (res->flags & IORESOURCE_IO)
lpc_open_pmio_window(res->base, res->size);
if (res->flags & IORESOURCE_MEM) {
/* Check if this is already decoded. */
if (lpc_fits_fixed_mmio_window(res->base, res->size))
continue;
lpc_open_mmio_window(res->base, res->size);
}
}
pch_lpc_set_child_resources(dev);
}

22
src/soc/intel/common/block/lpc/lpc_lib.c
View File

@ -148,28 +148,6 @@ void lpc_open_mmio_window(uintptr_t base, size_t size)
pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr);
}
bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size)
{
resource_t res_end, range_end;
const struct lpc_mmio_range *range;
const struct lpc_mmio_range *lpc_fixed_mmio_ranges =
soc_get_fixed_mmio_ranges();
for (range = lpc_fixed_mmio_ranges; range->size; range++) {
range_end = range->base + range->size;
res_end = base + size;
if ((base >= range->base) && (res_end <= range_end)) {
printk(BIOS_DEBUG,
"Resource %lx size %zx fits in fixed window"
" %lx size %zx\n",
base, size, range->base, range->size);
return true;
}
}
return false;
}
/*
* Set FAST_SPIBAR BIOS Control register based on input bit field.
*/

14
src/soc/intel/elkhartlake/espi.c
View File

@ -17,20 +17,6 @@
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
/*
* To reserve certain memory range as reserved range for BIOS usage.
* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
*/
static const struct lpc_mmio_range ehl_lpc_fixed_mmio_ranges[] = {
{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
{ 0, 0 }
};
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
{
return ehl_lpc_fixed_mmio_ranges;
}
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();

15
src/soc/intel/icelake/espi.c
View File

@ -17,21 +17,6 @@
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
/*
* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
* certain memory range as reserved range for BIOS usage.
* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
*/
static const struct lpc_mmio_range icl_lpc_fixed_mmio_ranges[] = {
{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
{ 0, 0 }
};
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
{
return icl_lpc_fixed_mmio_ranges;
}
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();

15
src/soc/intel/jasperlake/espi.c
View File

@ -17,21 +17,6 @@
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
/*
* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
* certain memory range as reserved range for BIOS usage.
* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
*/
static const struct lpc_mmio_range jsl_lpc_fixed_mmio_ranges[] = {
{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
{ 0, 0 }
};
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
{
return jsl_lpc_fixed_mmio_ranges;
}
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();

14
src/soc/intel/skylake/lpc.c
View File

@ -15,20 +15,6 @@
#include "chip.h"
/**
PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF
**/
static const struct lpc_mmio_range skl_lpc_fixed_mmio_ranges[] = {
{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
{ 0, 0 }
};
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
{
return skl_lpc_fixed_mmio_ranges;
}
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();

15
src/soc/intel/tigerlake/espi.c
View File

@ -23,21 +23,6 @@
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
/*
* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
* certain memory range as reserved range for BIOS usage.
* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
*/
static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = {
{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
{ 0, 0 }
};
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
{
return tgl_lpc_fixed_mmio_ranges;
}
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();

9
src/soc/intel/xeon_sp/lpc.c
View File

@ -9,15 +9,6 @@
#include <chip.h>
static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = {
{ 0, 0 }
};
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
{
return xeon_lpc_fixed_mmio_ranges;
}
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();