soc/mediatek/mt8192: move DFD driver to common folder

Move DFD driver to common folder so MT8195 can also use it.

BUG=b:192429713
TEST=emerge-asurada coreboot

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7937cddf5f3a66f9269a94301d3134e6f4f9f22e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/soc/mediatek/common/Kconfig

@@ -40,4 +40,10 @@ config DPM_FOUR_CHANNEL
 	help
 	  This option enables four channel configuration for DPM.
 
+config MTK_DFD
+	bool
+	default n
+	help
+	  This option enables DFD (Design for Debug) settings.
+
 endif

src/soc/mediatek/common/dfd.c

@@ -6,7 +6,7 @@
 
 void dfd_init(void)
 {
-	printk(BIOS_INFO, "[%s]\n", __func__);
+	printk(BIOS_INFO, "%s: enable DFD (Design For Debug)\n", __func__);
 	setbits32(dfd_cfg, RESET_ON_KEEP_EN);
 	dsb();
 }

src/soc/mediatek/common/include/soc/dfd_common.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_DFD_COMMON_H
+#define SOC_MEDIATEK_DFD_COMMON_H
+
+#define CPC_FLOW_CTRL_CFG	0x0C53A814
+#define RESET_ON_KEEP_EN	BIT(17)
+
+static u32 *const dfd_cfg = (void *)CPC_FLOW_CTRL_CFG;
+
+void dfd_init(void);
+
+#endif

src/soc/mediatek/mt8192/Kconfig

@@ -64,10 +64,4 @@ config SRCLKEN_RC_SUPPORT
 	  This option enables clock buffer remote controller module
 	  to control PMIC 26MHz clock output.
 
-config MTK_DFD
-	bool
-	default n
-	help
-	  This option enables DFD (Design for Debug) settings.
-
 endif

src/soc/mediatek/mt8192/Makefile.inc

@@ -46,7 +46,7 @@ ramstage-y += apusys.c
 ramstage-y += ../common/auxadc.c
 ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += devapc.c
-ramstage-y += dfd.c
+ramstage-y += ../common/dfd.c
 ramstage-y += ../common/dpm.c
 ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
 ramstage-y += ../common/flash_controller.c

src/soc/mediatek/mt8192/include/soc/dfd.h

@@ -3,15 +3,10 @@
 #ifndef SOC_MEDIATEK_MT8192_DFD_H
 #define SOC_MEDIATEK_MT8192_DFD_H
 
-#define CPC_FLOW_CTRL_CFG       0x0C53A814
+#include <soc/dfd_common.h>
-#define RESET_ON_KEEP_EN        BIT(17)
 
 /* DFD dump address and size need to be the same as defined in Kernel DTS. */
 #define DFD_DUMP_ADDRESS	0x6A000000
 #define DFD_DUMP_SIZE		(1 * MiB)
 
-static u32 *const dfd_cfg = (void *)CPC_FLOW_CTRL_CFG;
-
-void dfd_init(void);
-
 #endif