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mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin 

In order to pass DB type-C Port 1 USB2 eye diagram, DB USB2 PHY register needs
to be overridden.

port#1
PortUsb20Enable=1
Usb2PhyPetxiset=3
Usb2PhyTxiset=2
Usb2PhyPredeemp=7
Usb2PhyPehalfbit=1

BUG=b:173676539
BRANCH=None
TEST=emerge-volteer coreboot chromeos-bootimage

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
FrankChu 2020-12-01 09:54:00 +08:00 committed by Tim Wawrzynczak
parent ecf06e5e75
commit 71761a3838
1 changed files with 8 additions and 0 deletions
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8
src/mainboard/google/volteer/variants/delbin/overridetree.cb
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@ -44,6 +44,14 @@ chip soc/intel/tigerlake
},
},
}"
#These settings improve the USB2 Port1 eye diagram
register "usb2_ports[3]" = "{
.enable = 1,
.tx_bias = USB2_BIAS_28P15MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_56P3MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}"
# Acoustic settings
register "AcousticNoiseMitigation" = "1"