aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INIT
With implementation of LATE_CBMEM_INIT, top-of-low-memory TOLM was adjusted late in ramstage. We do not allow that with EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO space is now used with statically set TOLM. Also remove support code for the obsolete LATE_CBMEM_INIT this northbridge used. Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki
parent
9e69c87317
commit
717b6e3151
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@ -63,26 +63,3 @@ asmlinkage void romstage_after_car(void)
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/* Load the ramstage. */
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run_ramstage();
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}
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#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
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/* setup_stack_and_mtrrs() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use. */
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void *setup_stack_and_mtrrs(void)
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{
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struct postcar_frame pcf;
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postcar_frame_init_lowmem(&pcf);
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/* Cache the ROM as WP just below 4GiB. */
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postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
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MTRR_TYPE_WRPROT);
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Save the number of MTRRs to setup. Return the stack location
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* pointing to the number of MTRRs.
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*/
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return postcar_commit_mtrrs(&pcf);
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}
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#endif /* CONFIG_LATE_CBMEM_INIT */
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@ -18,6 +18,7 @@
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#include <arch/io.h>
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#include <arch/cpu.h>
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#include <stdlib.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <cpu/x86/bist.h>
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#include <cpu/intel/romstage.h>
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@ -77,4 +78,6 @@ void mainboard_romstage_entry(unsigned long bist)
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}
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printk(BIOS_DEBUG, "SDRAM is up.\n");
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cbmem_recovery(0);
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}
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@ -22,7 +22,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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def_bool y
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select NO_MMCONF_SUPPORT
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select HAVE_DEBUG_RAM_SETUP
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select LATE_CBMEM_INIT
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config HW_SCRUBBER
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bool
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@ -1,7 +1,9 @@
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ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7505),y)
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ramstage-y += northbridge.c
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ramstage-y += memmap.c
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romstage-y += raminit.c
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romstage-y += debug.c
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romstage-y += memmap.c
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endif
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@ -0,0 +1,66 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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#include <arch/io.h>
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#include <arch/cpu.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <cpu/intel/romstage.h>
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#include <cpu/x86/mtrr.h>
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#include <program_loading.h>
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#include "e7505.h"
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void *cbmem_top(void)
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{
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pci_devfn_t mch = PCI_DEV(0, 0, 0);
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uintptr_t tolm;
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/* This is at 128 MiB boundary. */
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tolm = pci_read_config16(mch, TOLM) >> 11;
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tolm <<= 27;
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return (void *)tolm;
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}
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#define ROMSTAGE_RAM_STACK_SIZE 0x5000
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/* setup_stack_and_mtrrs() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use. */
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void *setup_stack_and_mtrrs(void)
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
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die("Unable to initialize postcar frame.\n");
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/* Cache the ROM as WP just below 4GiB. */
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postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
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MTRR_TYPE_WRPROT);
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache CBMEM region as WB. */
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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/* Save the number of MTRRs to setup. Return the stack location
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* pointing to the number of MTRRs.
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*/
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return postcar_commit_mtrrs(&pcf);
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}
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@ -31,84 +31,43 @@ unsigned long acpi_fill_mcfg(unsigned long current)
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static void mch_domain_read_resources(struct device *dev)
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{
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int idx;
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unsigned long tomk, tolmk;
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unsigned long remapbasek, remaplimitk;
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const unsigned long basek_4G = 4 * (GiB / KiB);
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struct device *mc_dev;
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uint32_t pci_tolm;
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pci_domain_read_resources(dev);
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pci_tolm = find_pci_tolm(dev->link_list);
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mc_dev = dev->link_list->children;
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if (mc_dev) {
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/* Figure out which areas are/should be occupied by RAM.
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* This is all computed in kilobytes and converted to/from
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* the memory controller right at the edges.
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* Having different variables in different units is
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* too confusing to get right. Kilobytes are good up to
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* 4 Terabytes of RAM...
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*/
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uint16_t tolm_r, remapbase_r, remaplimit_r;
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unsigned long tomk, tolmk;
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unsigned long remapbasek, remaplimitk;
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int idx;
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mc_dev = dev_find_slot(0, PCI_DEVFN(0x0, 0));
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if (!mc_dev)
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die("Could not find MCH device\n");
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/* Get the value of the highest DRB. This tells the end of
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* the physical memory. The units are ticks of 64MB
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* i.e. 1 means 64MB.
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*/
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tomk = ((unsigned long)pci_read_config8(mc_dev, DRB_ROW_7)) << 16;
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/* Compute the top of Low memory */
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tolmk = pci_tolm >> 10;
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if (tolmk >= tomk) {
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/* The PCI hole does not overlap memory
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* we won't use the remap window.
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*/
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tolmk = tomk;
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remapbasek = 0x3ff << 16;
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remaplimitk = 0 << 16;
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}
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else {
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/* The PCI memory hole overlaps memory
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* setup the remap window.
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*/
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/* Find the bottom of the remap window
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* is it above 4G?
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*/
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remapbasek = 4*1024*1024;
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if (tomk > remapbasek) {
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remapbasek = tomk;
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}
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/* Find the limit of the remap window */
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remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
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}
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/* Write the RAM configuration registers,
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* preserving the reserved bits.
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*/
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tolm_r = pci_read_config16(mc_dev, TOLM);
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tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
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pci_write_config16(mc_dev, TOLM, tolm_r);
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tolmk = pci_read_config16(mc_dev, TOLM) >> 11;
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tolmk <<= 17;
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remapbase_r = pci_read_config16(mc_dev, REMAPBASE);
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remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
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pci_write_config16(mc_dev, REMAPBASE, remapbase_r);
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tomk = pci_read_config8(mc_dev, DRB_ROW_7);
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tomk <<= 16;
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remaplimit_r = pci_read_config16(mc_dev, REMAPLIMIT);
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remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
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pci_write_config16(mc_dev, REMAPLIMIT, remaplimit_r);
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/* Remapped region with a 64 MiB granularity in register
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definition. Limit is inclusive, so add one. */
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remapbasek = pci_read_config16(mc_dev, REMAPBASE) & 0x3ff;
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remapbasek <<= 16;
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/* Report the memory regions */
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idx = 10;
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ram_resource(dev, idx++, 0, 640);
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ram_resource(dev, idx++, 768, tolmk - 768);
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if (tomk > 4*1024*1024) {
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ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
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}
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if (remaplimitk >= remapbasek) {
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ram_resource(dev, idx++, remapbasek,
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(remaplimitk + 64*1024) - remapbasek);
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}
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remaplimitk = pci_read_config16(mc_dev, REMAPLIMIT) & 0x3ff;
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remaplimitk += 1;
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remaplimitk <<= 16;
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set_late_cbmem_top(tolmk * 1024);
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}
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/* Report the memory regions */
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idx = 10;
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ram_resource(dev, idx++, 0, 640);
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ram_resource(dev, idx++, 768, tolmk - 768);
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if (tomk > basek_4G)
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ram_resource(dev, idx++, basek_4G, tomk - basek_4G);
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if (remaplimitk > remapbasek)
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ram_resource(dev, idx++, remapbasek, remaplimitk - remapbasek);
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}
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static void mch_domain_set_resources(struct device *dev)
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@ -30,8 +30,8 @@
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#include <arch/cpu.h>
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#include <lib.h>
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#include <stdlib.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/msr.h>
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@ -850,6 +850,12 @@ static void configure_e7501_ram_addresses(const struct mem_controller
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{
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int i;
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uint8_t total_dram_64M_multiple = 0;
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uint64_t tolm, tom;
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uint16_t reg;
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/* Start with disabled remap range. */
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uint16_t remapbase_r = 0x3ff;
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uint16_t remaplimit_r = 0;
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// Configure the E7501's DRAM row boundaries
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// Start by zeroing out the temporary initial configuration
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@ -879,71 +885,37 @@ static void configure_e7501_ram_addresses(const struct mem_controller
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configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
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}
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// Configure the Top Of Low Memory (TOLM) in the E7501
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// This address must be a multiple of 128 MB that is less than 4 GB.
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// NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address
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// in the highest 5 bits.
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tom = total_dram_64M_multiple * 64ULL * MiB;
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// We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system.
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// This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes
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// such as flash and memory-mapped I/O.
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/* Reserve MMIO space. */
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tolm = 4ULL * GiB - 1 * GiB;
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tolm = MIN(tolm, tom);
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// If there is more than 3 GB of DRAM, we define a remap window which
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// makes the DRAM "behind" the reserved region available above the top of physical
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// memory.
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/* The PCI memory hole overlaps memory setup the remap window. */
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if (tolm < tom) {
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uint64_t remapbase = MAX(tom, 4ULL * GiB);
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uint64_t remaplimit = remapbase + (4ULL * GiB - tolm);
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// NOTE: 0xC0000000 / (64 MB) == 0x30
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remapbase_r = remapbase / (64 * MiB);
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remaplimit_r = remaplimit / (64 * MiB);
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if (total_dram_64M_multiple <= 0x30) {
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// <= 3 GB total RAM
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/* I should really adjust all of this in C after I have resources
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* to all of the pci devices.
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*/
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// Round up to 128MB granularity
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// SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?
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uint8_t total_dram_128M_multiple =
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(total_dram_64M_multiple + 1) >> 1;
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// Convert to high 16 bits of address
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uint16_t top_of_low_memory =
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total_dram_128M_multiple << 11;
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pci_write_config16(MCHDEV, TOLM,
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top_of_low_memory);
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} else {
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// > 3 GB total RAM
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// Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory
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uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0
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uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF
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// Put TOLM at 3 GB
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pci_write_config16(MCHDEV, TOLM, 0xc000);
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// Define a remap window to make the RAM that would appear from 3 GB - 4 GB
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// visible just beyond 4 GB or the end of physical memory, whichever is larger
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// NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address,
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// (i.e. a multiple of 64 MB) in the lowest 10 bits.
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// NOTE: 0x100000000 / (64 MB) == 0x40
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if (total_dram_64M_multiple < 0x40) {
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remap_base = 0x40; // 0x100000000
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remap_limit =
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0x40 + (total_dram_64M_multiple - 0x30) - 1;
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}
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pci_write_config16(MCHDEV, REMAPBASE,
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remap_base);
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pci_write_config16(MCHDEV, REMAPLIMIT,
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remap_limit);
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/* Limit register is inclusive. */
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remaplimit_r -= 1;
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}
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/* Write the RAM configuration registers,
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preserving the reserved bits. */
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reg = pci_read_config16(MCHDEV, TOLM) & 0x7ff;
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reg |= (tolm / (128 * MiB)) << 11;
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pci_write_config16(MCHDEV, TOLM, reg);
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reg = pci_read_config16(MCHDEV, REMAPBASE) & 0xfc00;
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reg |= remapbase_r;
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pci_write_config16(MCHDEV, REMAPBASE, reg);
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reg = pci_read_config16(MCHDEV, REMAPLIMIT) & 0xfc00;
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reg |= remaplimit_r;
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pci_write_config16(MCHDEV, REMAPLIMIT, reg);
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}
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/**
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@ -1904,12 +1876,6 @@ void e7505_mch_init(const struct mem_controller *memctrl)
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sdram_enable(memctrl);
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}
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uintptr_t restore_top_of_low_cacheable(void)
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{
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u32 tolm = (pci_read_config16(MCHDEV, TOLM) & ~0x7ff) << 16;
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return tolm;
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}
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/**
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* Scrub and reset error counts for ECC dimms.
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*
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