diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 0c9325da41..2ee273c1f4 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -62,7 +62,6 @@ static void sandybridge_setup_bars(void)
 
 static void sandybridge_setup_graphics(void)
 {
-	u32 reg32;
 	u16 reg16;
 	u8 gfxsize;
 
@@ -106,27 +105,18 @@ static void sandybridge_setup_graphics(void)
 	pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02);
 
 	/* Erratum workarounds */
-	reg32 = MCHBAR32(SAPMCTL);
-	reg32 |= (1 << 9) | (1 << 10);
-	MCHBAR32(SAPMCTL) = reg32;
+	MCHBAR32_OR(SAPMCTL, (1 << 9) | (1 << 10));
 
 	/* Enable SA Clock Gating */
-	reg32 = MCHBAR32(SAPMCTL);
-	MCHBAR32(SAPMCTL) = reg32 | 1;
+	MCHBAR32_OR(SAPMCTL, 1);
 
 	/* GPU RC6 workaround for sighting 366252 */
-	reg32 = MCHBAR32(SSKPD_HI);
-	reg32 |= (1 << 31);
-	MCHBAR32(SSKPD_HI) = reg32;
+	MCHBAR32_OR(SSKPD_HI, 1 << 31);
 
 	/* VLW (Virtual Legacy Wire?) */
-	reg32 = MCHBAR32(0x6120);
-	reg32 &= ~(1 << 0);
-	MCHBAR32(0x6120) = reg32;
+	MCHBAR32_AND(0x6120, ~(1 << 0));
 
-	reg32 = MCHBAR32(INTRDIRCTL);
-	reg32 |= (1 << 4) | (1 << 5);
-	MCHBAR32(INTRDIRCTL) = reg32;
+	MCHBAR32_OR(INTRDIRCTL, (1 << 4) | (1 << 5));
 }
 
 static void start_peg_link_training(void)