reset: Finalize move to new API

Move soft_reset() to `southbridge/amd/common/` it's only used for
amdfam10 now.

Drop hard_reset() for good.

Change-Id: Ifdc5791160653c5578007f6c1b96015efe2b3e1e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/Kconfig

@@ -449,13 +449,6 @@ config RESUME_PATH_SAME_AS_BOOT
 	  same path as a regular boot. e.g. an x86 system runs from the
 	  reset vector at 0xfffffff0 on both resume and warm/cold boot.
 
-config HAVE_HARD_RESET
-	bool
-	default n
-	help
-	  This variable specifies whether a given board has a hard_reset
-	  function, no matter if it's provided by board code or chipset code.
-
 config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
 	bool
 	depends on EARLY_CBMEM_INIT

src/cpu/amd/family_10h-family_15h/init_cpus.c

@@ -27,6 +27,8 @@
 #include <northbridge/amd/amdht/porting.h>
 #include <northbridge/amd/amdht/h3ncmn.h>
 
+#include <southbridge/amd/common/reset.h>
+
 #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700)
 #include <southbridge/amd/sb700/sb700.h>
 #endif

src/include/reset.h

@@ -39,14 +39,4 @@ __noreturn void board_reset(void);
  */
 void do_board_reset(void);
 
-/* Full board reset. Resets SoC and most/all board components (e.g. DRAM). */
-__noreturn void hard_reset(void);
-/* Board reset. Resets SoC some board components (e.g. TPM but not DRAM). */
-__noreturn void soft_reset(void);
-
-/* Reset implementations. Implement these in SoC or mainboard code. Implement
-   at least hard_reset() if possible, others fall back to it if necessary. */
-void do_hard_reset(void);
-void do_soft_reset(void);
-
 #endif

src/lib/reset.c

@@ -31,39 +31,4 @@ void do_board_reset(void)
 {
 	printk(BIOS_CRIT, "No board_reset implementation, hanging...\n");
 }
-#else
-/*
- * Fall back to hard_reset() for a regression free transition.
- * FIXME: Remove after everything is converted to board_reset().
- */
-__weak void do_board_reset(void)
-{
-	hard_reset();
-}
 #endif
-
-__noreturn static void __hard_reset(void) {
-	if (IS_ENABLED(CONFIG_HAVE_HARD_RESET))
-		do_hard_reset();
-	else
-		printk(BIOS_CRIT, "No hard_reset implementation, hanging...\n");
-	halt();
-}
-
-/* Not all platforms implement all reset types. Fall back to hard_reset. */
-__weak void do_soft_reset(void) { __hard_reset(); }
-
-void hard_reset(void)
-{
-	printk(BIOS_INFO, "%s() called!\n", __func__);
-	dcache_clean_all();
-	__hard_reset();
-}
-
-void soft_reset(void)
-{
-	printk(BIOS_INFO, "%s() called!\n", __func__);
-	dcache_clean_all();
-	do_soft_reset();
-	halt();
-}

src/mainboard/advansus/a785e-i/romstage.c

@@ -40,6 +40,7 @@
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <northbridge/amd/amdht/ht_wrapper.h>
 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb800/smbus.h>
 #include <southbridge/amd/sb800/sb800.h>
 #include <southbridge/amd/rs780/rs780.h>
@@ -50,7 +51,6 @@
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"
 #include "spd.h"
-#include <reset.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 

src/mainboard/amd/bimini_fam10/romstage.c

@@ -36,6 +36,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb800/smbus.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <northbridge/amd/amdht/ht_wrapper.h>

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -40,6 +40,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>
 #include <northbridge/amd/amdfam10/raminit.h>

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -38,6 +38,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>
 #include <northbridge/amd/amdfam10/raminit.h>

src/mainboard/asus/kcma-d8/romstage.c

@@ -19,7 +19,6 @@
 
 #include <stdint.h>
 #include <string.h>
-#include <reset.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
@@ -39,6 +38,7 @@
 #include <smp/spinlock.h>
 #include <cpu/amd/car.h>
 #include <cpu/amd/msr.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>
 #include <southbridge/amd/sr5650/sr5650.h>

src/mainboard/asus/kfsn4-dre/romstage.c

@@ -22,7 +22,6 @@
 
 #include <stdint.h>
 #include <string.h>
-#include <reset.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
@@ -36,6 +35,7 @@
 #include <cpu/amd/model_10xxx_rev.h>
 #include <cpu/amd/car.h>
 #include <cpu/amd/msr.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/nvidia/ck804/early_smbus.h>
 #include <delay.h>
 #include <cpu/x86/lapic.h>

src/mainboard/asus/kgpe-d16/romstage.c

@@ -19,7 +19,6 @@
 
 #include <stdint.h>
 #include <string.h>
-#include <reset.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
@@ -39,6 +38,7 @@
 #include <cpu/amd/car.h>
 #include <cpu/amd/msr.h>
 #include <smp/spinlock.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>
 #include <southbridge/amd/sr5650/sr5650.h>

src/mainboard/asus/m4a78-em/romstage.c

@@ -39,6 +39,7 @@
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
 #include <cpu/amd/msr.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>
 #include <northbridge/amd/amdfam10/raminit.h>

src/mainboard/asus/m4a785-m/romstage.c

@@ -40,6 +40,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>
 #include <northbridge/amd/amdfam10/raminit.h>

src/mainboard/asus/m5a88-v/romstage.c

@@ -39,6 +39,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb800/smbus.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <northbridge/amd/amdht/ht_wrapper.h>
@@ -48,7 +49,6 @@
 #include <southbridge/amd/rs780/rs780.h>
 #include "southbridge/amd/sb800/early_setup.c"
 #include "spd.h"
-#include <reset.h>
 
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"

src/mainboard/avalue/eax-785e/romstage.c

@@ -37,6 +37,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb800/smbus.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <northbridge/amd/amdht/ht_wrapper.h>
@@ -44,7 +45,6 @@
 #include <arch/early_variables.h>
 #include <cbmem.h>
 #include "spd.h"
-#include <reset.h>
 #include <southbridge/amd/rs780/rs780.h>
 #include <southbridge/amd/sb800/early_setup.c>
 

src/mainboard/gigabyte/ma785gm/romstage.c

@@ -36,6 +36,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>
 #include <northbridge/amd/amdfam10/raminit.h>

src/mainboard/gigabyte/ma785gmt/romstage.c

@@ -36,6 +36,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>
 #include <northbridge/amd/amdfam10/raminit.h>

src/mainboard/gigabyte/ma78gm/romstage.c

@@ -39,6 +39,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>
 #include <spd.h>

src/mainboard/hp/dl165_g6_fam10/romstage.c

@@ -49,6 +49,7 @@
 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
 #include <arch/early_variables.h>
 #include <cbmem.h>
+#include <southbridge/amd/common/reset.h>
 #include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "southbridge/broadcom/bcm5785/early_setup.c"
 

src/mainboard/iei/kino-780am2-fam10/romstage.c

@@ -39,6 +39,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>
 #include <spd.h>

src/mainboard/jetway/pa78vm5/romstage.c

@@ -40,6 +40,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>
 #include <spd.h>

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -42,6 +42,7 @@
 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
 #include <arch/early_variables.h>
 #include <cbmem.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/nvidia/mcp55/mcp55.h>
 
 #include "resourcemap.c"

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -37,6 +37,7 @@
 #include <cpu/x86/bist.h>
 #include <cpu/amd/car.h>
 #include <cpu/amd/msr.h>
+#include <southbridge/amd/common/reset.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <northbridge/amd/amdht/ht_wrapper.h>
 #include <cpu/amd/family_10h-family_15h/init_cpus.h>

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -37,6 +37,7 @@
 #include <cpu/x86/bist.h>
 #include <cpu/amd/car.h>
 #include <cpu/amd/msr.h>
+#include <southbridge/amd/common/reset.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <northbridge/amd/amdht/ht_wrapper.h>
 #include <cpu/amd/family_10h-family_15h/init_cpus.h>

src/mainboard/supermicro/h8scm_fam10/romstage.c

@@ -37,6 +37,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
+#include <southbridge/amd/common/reset.h>
 #include <southbridge/amd/sb700/sb700.h>
 #include <southbridge/amd/sb700/smbus.h>
 #include <southbridge/amd/sr5650/sr5650.h>

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -37,6 +37,7 @@
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627hf/w83627hf.h>
 #include <cpu/x86/bist.h>
+#include <southbridge/amd/common/reset.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <northbridge/amd/amdht/ht_wrapper.h>
 #include <cpu/amd/family_10h-family_15h/init_cpus.h>

src/northbridge/amd/amdmct/mct_ddr3/mct_d.c

@@ -36,7 +36,7 @@
 #include <northbridge/amd/amdfam10/debug.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <northbridge/amd/amdfam10/amdfam10.h>
-#include <reset.h>
+#include <southbridge/amd/common/reset.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
 #include <arch/acpi.h>

src/security/vboot/Kconfig

@@ -18,7 +18,7 @@ config VBOOT
 	bool "Verify firmware with vboot."
 	default n
 	select VBOOT_MOCK_SECDATA if !TPM1 && !TPM2
-	depends on HAVE_HARD_RESET || !MISSING_BOARD_RESET
+	depends on !MISSING_BOARD_RESET
 	help
 	  Enabling VBOOT will use vboot to verify the components of the firmware
 	  (stages, payload, etc).

src/southbridge/amd/amd8111/early_ctrl.c

@@ -15,6 +15,7 @@
 
 #include "amd8111.h"
 #include <reset.h>
+#include <southbridge/amd/common/reset.h>
 
 unsigned get_sbdn(unsigned bus)
 {

src/southbridge/amd/common/reset.h

@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _AMD_SB_RESET_H_
+#define _AMD_SB_RESET_H_
+
+#include <arch/cache.h>
+#include <console/console.h>
+#include <halt.h>
+
+/* Implement the bare reset, e.g. write to cf9. */
+void do_soft_reset(void);
+
+/* Prepare for reset, run do_soft_reset(), halt. */
+static inline __noreturn void soft_reset(void)
+{
+	printk(BIOS_INFO, "%s() called!\n", __func__);
+	dcache_clean_all();
+	do_soft_reset();
+	halt();
+}
+
+#endif	/* _AMD_SB_RESET_H_ */

src/southbridge/amd/sb700/reset.c

@@ -18,6 +18,7 @@
 
 #include <arch/io.h>
 #include <reset.h>
+#include <southbridge/amd/common/reset.h>
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)

src/southbridge/amd/sb800/early_setup.c

@@ -19,6 +19,7 @@
 #include <reset.h>
 #include <arch/cpu.h>
 #include <southbridge/amd/common/amd_defs.h>
+#include <southbridge/amd/common/reset.h>
 #include "sb800.h"
 #include "smbus.c"
 

src/southbridge/amd/sr5650/early_setup.c

@@ -22,7 +22,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
 #include <option.h>
-#include <reset.h>
+#include <southbridge/amd/common/reset.h>
 #include "sr5650.h"
 #include "cmn.h"
 

src/southbridge/broadcom/bcm5785/early_setup.c

@@ -15,6 +15,7 @@
  */
 
 #include <reset.h>
+#include <southbridge/amd/common/reset.h>
 #include "bcm5785.h"
 
 static void bcm5785_enable_lpc(void)

src/southbridge/nvidia/ck804/early_setup.c

@@ -15,6 +15,7 @@
  */
 
 #include <reset.h>
+#include <southbridge/amd/common/reset.h>
 #include "ck804.h"
 
 static int set_ht_link_ck804(u8 ht_c_num)

src/southbridge/nvidia/ck804/early_setup_car.c

@@ -16,6 +16,7 @@
  * GNU General Public License for more details.
  */
 
+#include <southbridge/amd/common/reset.h>
 #include "ck804.h"
 
 /* Someone messed up and snuck in some K8-specific code */

src/southbridge/nvidia/mcp55/early_ctrl.c

@@ -19,6 +19,7 @@
 #include <console/console.h>
 #include <reset.h>
 #include <northbridge/amd/amdfam10/amdfam10.h>
+#include <southbridge/amd/common/reset.h>
 #include "mcp55.h"
 
 void do_soft_reset(void)