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nb/intel/sandybridge: Drop write_controller_mr() function 

The only reason to write the MR values to the training result registers
is for EV (Electrical Validation) usage. The hardware doesn't need it.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: I808174494729453f4ebcaa13258d735faae68d72
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-11-11 19:01:28 +01:00 committed by Patrick Georgi
parent 2f3cc0035d
commit 71902014e3
3 changed files with 0 additions and 15 deletions
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12
src/northbridge/intel/sandybridge/raminit_common.c
View File

@ -4078,18 +4078,6 @@ void normalize_training(ramctr_timing *ctrl)
} }
} }
void write_controller_mr(ramctr_timing *ctrl)
{
int channel, slotrank;
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT1(channel)) =
make_mr0(ctrl, slotrank);
MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT2(channel)) =
make_mr1(ctrl, slotrank, channel);
}
}
int channel_test(ramctr_timing *ctrl) int channel_test(ramctr_timing *ctrl)
{ {
int channel, slotrank, lane; int channel, slotrank, lane;

1
src/northbridge/intel/sandybridge/raminit_common.h
View File

@ -244,7 +244,6 @@ int discover_edges(ramctr_timing *ctrl);
int discover_edges_write(ramctr_timing *ctrl); int discover_edges_write(ramctr_timing *ctrl);
int discover_timC_write(ramctr_timing *ctrl); int discover_timC_write(ramctr_timing *ctrl);
void normalize_training(ramctr_timing *ctrl); void normalize_training(ramctr_timing *ctrl);
void write_controller_mr(ramctr_timing *ctrl);
int channel_test(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl);
void set_scrambling_seed(ramctr_timing *ctrl); void set_scrambling_seed(ramctr_timing *ctrl);
void set_wmm_behavior(const u32 cpu); void set_wmm_behavior(const u32 cpu);

2
src/northbridge/intel/sandybridge/raminit_native.c
View File

@ -715,8 +715,6 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_
set_read_write_timings(ctrl); set_read_write_timings(ctrl);
write_controller_mr(ctrl);
if (!s3resume) { if (!s3resume) {
err = channel_test(ctrl); err = channel_test(ctrl);
if (err) if (err)