* drop ich7 include
* detect more i945 variants * raminit fixes * ACPI + PCIe updates Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
4da810bd53
commit
71a3d96bc4
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@ -22,5 +22,8 @@ uses CONFIG_HAVE_HIGH_TABLES
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default CONFIG_HAVE_HIGH_TABLES=1
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config chip.h
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object acpi.o
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driver northbridge.o
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driver gma.o
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@ -0,0 +1,74 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <types.h>
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#include <string.h>
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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device_t dev;
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u32 pciexbar = 0;
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u32 pciexbar_reg;
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int max_buses;
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dev = dev_find_device(0x8086, 0x27a0, 0);
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if (!dev)
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return current;
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pciexbar_reg=pci_read_config32(dev, 0x48);
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// MMCFG not supported or not enabled.
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if (!(pciexbar_reg & (1 << 0)))
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return current;
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switch ((pciexbar_reg >> 1) & 3) {
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case 0: // 256MB
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pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
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max_buses = 256;
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break;
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case 1: // 128M
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pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
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max_buses = 128;
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break;
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case 2: // 64M
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pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
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max_buses = 64;
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break;
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default: // RSVD
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return current;
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}
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if (!pciexbar)
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return current;
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
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pciexbar, 0x0, 0x0, max_buses - 1);
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return current;
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}
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@ -26,35 +26,50 @@ Device (PDRC)
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{
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Name (_HID, EISAID("PNP0C02"))
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Name (_UID, 1)
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// This does not seem to work correctly yet - set values statically for
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// now.
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//Name (PDRS, ResourceTemplate() {
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// Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
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// Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
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// Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
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// Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
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// Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
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// Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
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//})
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Name (PDRS, ResourceTemplate() {
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Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
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Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
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Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
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Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
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Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
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Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
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Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
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Memory32Fixed(ReadWrite, 0xfed14000, 0x00004000) // MCHBAR
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Memory32Fixed(ReadWrite, 0xfed18000, 0x00001000) // DMIBAR
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Memory32Fixed(ReadWrite, 0xfed19000, 0x00001000) // EPBAR
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Memory32Fixed(ReadWrite, 0xf0000000, 0x04000000) // PCIE BAR
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Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
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Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
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Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
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})
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// Current Resource Settings
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Method (_CRS, 0, Serialized)
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{
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CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
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ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
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//CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
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//ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
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CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
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ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
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//CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
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//ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
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CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
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ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
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//CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
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//ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
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CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
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ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
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//CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
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//ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
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CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
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ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
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//CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
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//ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
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CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
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ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
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//CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
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//ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
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Return(PDRS)
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}
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@ -35,18 +35,18 @@ Device (MCHC)
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, 11, //
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EPBR, 20, // EPBAR
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Offset (0x48), // MCHBAR
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Offset (0x44), // MCHBAR
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MHEN, 1, // Enable
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, 13, //
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MHBR, 18, // MCHBAR
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Offset (0x60), // PCIe BAR
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Offset (0x48), // PCIe BAR
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PXEN, 1, // Enable
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PXSZ, 2, // BAR size
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, 23, //
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PXBR, 6, // PCIe BAR
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Offset (0x68), // DMIBAR
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Offset (0x4c), // DMIBAR
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DMEN, 1, // Enable
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, 11, //
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DMBR, 20, // DMIBAR
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@ -87,11 +87,13 @@ Device (MCHC)
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, 2,
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PM6H, 2,
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, 2,
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Offset (0xa2), // Top of upper used dram
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TUUD, 16,
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Offset (0xb0),
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, 4,
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TLUD, 12 // TOLUD
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Offset (0x9c), // Top of Low Used Memory
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, 3,
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TLUD, 5,
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Offset (0xa0), // Top of Used Memory
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TOM, 16,
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}
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}
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@ -172,11 +174,29 @@ Method (_CRS, 0, Serialized)
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0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
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0x00004000,,, OPR7)
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// Bios Extension (0xe0000-0xeffff)
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// BIOS Extension (0xe0000-0xe3fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e0000, 0x000effff, 0x00000000,
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0x00010000,,, ESEG)
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0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
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0x00004000,,, ESG0)
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// BIOS Extension (0xe4000-0xe7fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
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0x00004000,,, ESG1)
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// BIOS Extension (0xe8000-0xebfff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
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0x00004000,,, ESG2)
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// BIOS Extension (0xec000-0xeffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000ec000, 0x000effff, 0x00000000,
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0x00004000,,, ESG3)
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// System BIOS (0xf0000-0xfffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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@ -189,6 +209,12 @@ Method (_CRS, 0, Serialized)
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Cacheable, ReadWrite,
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0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
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0x00000000,,, PM01)
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// TPM Area (0xfed40000-0xfed44fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
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0x00000000,,, TPMR)
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})
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// Find PCI resource area in MCRS
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@ -197,64 +223,15 @@ Method (_CRS, 0, Serialized)
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CreateDwordField(MCRS, PM01._LEN, PLEN)
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// Fix up PCI memory region:
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// Enter actual TOLUD. The TOLUD register contains bits 20-31 of
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// Enter actual TOLUD. The TOLUD register contains bits 27-31 of
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// the top of memory address.
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ShiftLeft (^MCHC.TLUD, 20, PMIN)
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ShiftLeft (^MCHC.TLUD, 27, PMIN)
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Add(Subtract(PMAX, PMIN), 1, PLEN)
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Return (MCRS)
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}
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// PCI Interrupt Routing
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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// PCIe Graphics 0:1.0
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Package() { 0x0001ffff, 0, 0, 16 },
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, 0, 16 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, 0, 16 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, 0, 16 },
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Package() { 0x001cffff, 1, 0, 17 },
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Package() { 0x001cffff, 2, 0, 18 },
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Package() { 0x001cffff, 3, 0, 19 },
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// USB and EHCI 0:1d.x
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Package() { 0x001dffff, 0, 0, 23 },
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Package() { 0x001dffff, 1, 0, 19 },
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Package() { 0x001dffff, 2, 0, 18 },
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Package() { 0x001dffff, 3, 0, 16 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, 0, 19 },
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Package() { 0x001fffff, 1, 0, 19},
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Package() { 0x001fffff, 2, 0, 19 },
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Package() { 0x001fffff, 3, 0, 16 }
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})
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} Else {
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Return (Package() {
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// PCIe Graphics 0:1.0
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Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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// USB and EHCI 0:1d.x
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
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Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
|
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})
|
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}
|
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/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
|
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Include ("acpi/i945_pci_irqs.asl")
|
||||
|
||||
|
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}
|
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|
|
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|
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@ -23,6 +23,302 @@ Device (GFX0)
|
|||
{
|
||||
Name (_ADR, 0x00020000)
|
||||
|
||||
// TODO display switching etc
|
||||
/* Display Output Switching */
|
||||
Method (_DOS, 1)
|
||||
{
|
||||
/* Windows 2000 and Windows XP call _DOS to enable/disable
|
||||
* Display Output Switching during init and while a switch
|
||||
* is already active
|
||||
*/
|
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Store (And(Arg0, 7), DSEN)
|
||||
}
|
||||
|
||||
/* We try to support as many i945 systems as possible,
|
||||
* so keep the number of DIDs flexible.
|
||||
*/
|
||||
Method (_DOD, 0)
|
||||
{
|
||||
If (LEqual(NDID, 1)) {
|
||||
Name(DOD1, Package() {
|
||||
0xffffffff
|
||||
})
|
||||
Store (Or(0x00010000, DID1), Index(DOD1, 0))
|
||||
Return(DOD1)
|
||||
}
|
||||
|
||||
If (LEqual(NDID, 2)) {
|
||||
Name(DOD2, Package() {
|
||||
0xffffffff,
|
||||
0xffffffff
|
||||
})
|
||||
Store (Or(0x00010000, DID2), Index(DOD2, 0))
|
||||
Store (Or(0x00010000, DID2), Index(DOD2, 1))
|
||||
Return(DOD2)
|
||||
}
|
||||
|
||||
If (LEqual(NDID, 3)) {
|
||||
Name(DOD3, Package() {
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0xffffffff
|
||||
})
|
||||
Store (Or(0x00010000, DID3), Index(DOD3, 0))
|
||||
Store (Or(0x00010000, DID3), Index(DOD3, 1))
|
||||
Store (Or(0x00010000, DID3), Index(DOD3, 2))
|
||||
Return(DOD3)
|
||||
}
|
||||
|
||||
If (LEqual(NDID, 4)) {
|
||||
Name(DOD4, Package() {
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0xffffffff
|
||||
})
|
||||
Store (Or(0x00010000, DID4), Index(DOD4, 0))
|
||||
Store (Or(0x00010000, DID4), Index(DOD4, 1))
|
||||
Store (Or(0x00010000, DID4), Index(DOD4, 2))
|
||||
Store (Or(0x00010000, DID4), Index(DOD4, 3))
|
||||
Return(DOD4)
|
||||
}
|
||||
|
||||
If (LGreater(NDID, 4)) {
|
||||
Name(DOD5, Package() {
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0xffffffff
|
||||
})
|
||||
Store (Or(0x00010000, DID5), Index(DOD5, 0))
|
||||
Store (Or(0x00010000, DID5), Index(DOD5, 1))
|
||||
Store (Or(0x00010000, DID5), Index(DOD5, 2))
|
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Store (Or(0x00010000, DID5), Index(DOD5, 3))
|
||||
Store (Or(0x00010000, DID5), Index(DOD5, 4))
|
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Return(DOD5)
|
||||
}
|
||||
|
||||
/* Some error happened, but we have to return something */
|
||||
Return (Package() {0x00000400})
|
||||
}
|
||||
|
||||
Device(DD01)
|
||||
{
|
||||
/* Device Unique ID */
|
||||
Method(_ADR, 0, Serialized)
|
||||
{
|
||||
If(LEqual(DID1, 0)) {
|
||||
Return (1)
|
||||
} Else {
|
||||
Return (And(0xffff, DID1))
|
||||
}
|
||||
}
|
||||
|
||||
/* Device Current Status */
|
||||
Method(_DCS, 0)
|
||||
{
|
||||
TRAP(1)
|
||||
If (And(CSTE, 1)) {
|
||||
Return (0x1f)
|
||||
}
|
||||
Return(0x1d)
|
||||
}
|
||||
|
||||
/* Query Device Graphics State */
|
||||
Method(_DGS, 0)
|
||||
{
|
||||
If (And(NSTE, 1)) {
|
||||
Return(1)
|
||||
}
|
||||
Return(0)
|
||||
}
|
||||
|
||||
/* Device Set State */
|
||||
Method(_DSS, 1)
|
||||
{
|
||||
/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
|
||||
* display switch was completed
|
||||
*/
|
||||
If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
|
||||
Store (NSTE, CSTE)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Device(DD02)
|
||||
{
|
||||
/* Device Unique ID */
|
||||
Method(_ADR, 0, Serialized)
|
||||
{
|
||||
If(LEqual(DID2, 0)) {
|
||||
Return (2)
|
||||
} Else {
|
||||
Return (And(0xffff, DID2))
|
||||
}
|
||||
}
|
||||
|
||||
/* Device Current Status */
|
||||
Method(_DCS, 0)
|
||||
{
|
||||
TRAP(1)
|
||||
If (And(CSTE, 2)) {
|
||||
Return (0x1f)
|
||||
}
|
||||
Return(0x1d)
|
||||
}
|
||||
|
||||
/* Query Device Graphics State */
|
||||
Method(_DGS, 0)
|
||||
{
|
||||
If (And(NSTE, 2)) {
|
||||
Return(1)
|
||||
}
|
||||
Return(0)
|
||||
}
|
||||
|
||||
/* Device Set State */
|
||||
Method(_DSS, 1)
|
||||
{
|
||||
/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
|
||||
* display switch was completed
|
||||
*/
|
||||
If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
|
||||
Store (NSTE, CSTE)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Device(DD03)
|
||||
{
|
||||
/* Device Unique ID */
|
||||
Method(_ADR, 0, Serialized)
|
||||
{
|
||||
If(LEqual(DID3, 0)) {
|
||||
Return (3)
|
||||
} Else {
|
||||
Return (And(0xffff, DID3))
|
||||
}
|
||||
}
|
||||
|
||||
/* Device Current Status */
|
||||
Method(_DCS, 0)
|
||||
{
|
||||
TRAP(1)
|
||||
If (And(CSTE, 4)) {
|
||||
Return (0x1f)
|
||||
}
|
||||
Return(0x1d)
|
||||
}
|
||||
|
||||
/* Query Device Graphics State */
|
||||
Method(_DGS, 0)
|
||||
{
|
||||
If (And(NSTE, 4)) {
|
||||
Return(1)
|
||||
}
|
||||
Return(0)
|
||||
}
|
||||
|
||||
/* Device Set State */
|
||||
Method(_DSS, 1)
|
||||
{
|
||||
/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
|
||||
* display switch was completed
|
||||
*/
|
||||
If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
|
||||
Store (NSTE, CSTE)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Device(DD04)
|
||||
{
|
||||
/* Device Unique ID */
|
||||
Method(_ADR, 0, Serialized)
|
||||
{
|
||||
If(LEqual(DID4, 0)) {
|
||||
Return (4)
|
||||
} Else {
|
||||
Return (And(0xffff, DID4))
|
||||
}
|
||||
}
|
||||
|
||||
/* Device Current Status */
|
||||
Method(_DCS, 0)
|
||||
{
|
||||
TRAP(1)
|
||||
If (And(CSTE, 8)) {
|
||||
Return (0x1f)
|
||||
}
|
||||
Return(0x1d)
|
||||
}
|
||||
|
||||
/* Query Device Graphics State */
|
||||
Method(_DGS, 0)
|
||||
{
|
||||
If (And(NSTE, 4)) {
|
||||
Return(1)
|
||||
}
|
||||
Return(0)
|
||||
}
|
||||
|
||||
/* Device Set State */
|
||||
Method(_DSS, 1)
|
||||
{
|
||||
/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
|
||||
* display switch was completed
|
||||
*/
|
||||
If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
|
||||
Store (NSTE, CSTE)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Device(DD05)
|
||||
{
|
||||
/* Device Unique ID */
|
||||
Method(_ADR, 0, Serialized)
|
||||
{
|
||||
If(LEqual(DID5, 0)) {
|
||||
Return (5)
|
||||
} Else {
|
||||
Return (And(0xffff, DID5))
|
||||
}
|
||||
}
|
||||
|
||||
/* Device Current Status */
|
||||
Method(_DCS, 0)
|
||||
{
|
||||
TRAP(1)
|
||||
If (And(CSTE, 16)) {
|
||||
Return (0x1f)
|
||||
}
|
||||
Return(0x1d)
|
||||
}
|
||||
|
||||
/* Query Device Graphics State */
|
||||
Method(_DGS, 0)
|
||||
{
|
||||
If (And(NSTE, 4)) {
|
||||
Return(1)
|
||||
}
|
||||
Return(0)
|
||||
}
|
||||
|
||||
/* Device Set State */
|
||||
Method(_DSS, 1)
|
||||
{
|
||||
/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
|
||||
* display switch was completed
|
||||
*/
|
||||
If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
|
||||
Store (NSTE, CSTE)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ static int i945_silicon_revision(void)
|
|||
return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION);
|
||||
}
|
||||
|
||||
static void i945_detect_chipset(void)
|
||||
static void i945m_detect_chipset(void)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
|
|
@ -33,19 +33,19 @@ static void i945_detect_chipset(void)
|
|||
reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4;
|
||||
switch (reg8) {
|
||||
case 1:
|
||||
printk_info("Mobile Intel(R) 945GM/GME Express");
|
||||
printk_info("Mobile Intel(R) 82945GM/GME Express");
|
||||
break;
|
||||
case 2:
|
||||
printk_info("Mobile Intel(R) 945GMS/GU Express");
|
||||
printk_info("Mobile Intel(R) 82945GMS/GU Express");
|
||||
break;
|
||||
case 3:
|
||||
printk_info("Mobile Intel(R) 945PM Express");
|
||||
printk_info("Mobile Intel(R) 82945PM Express");
|
||||
break;
|
||||
case 5:
|
||||
printk_info("Intel(R) 945GT Express");
|
||||
printk_info("Intel(R) 82945GT Express");
|
||||
break;
|
||||
case 6:
|
||||
printk_info("Mobile Intel(R) 943/940GML Express");
|
||||
printk_info("Mobile Intel(R) 82943/82940GML Express");
|
||||
break;
|
||||
default:
|
||||
printk_info("Unknown (%02x)", reg8); /* Others reserved. */
|
||||
|
|
@ -87,6 +87,45 @@ static void i945_detect_chipset(void)
|
|||
printk_debug("\n");
|
||||
}
|
||||
|
||||
static void i945_detect_chipset(void)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
printk_info("\nIntel(R) ");
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0x8);
|
||||
switch (reg8) {
|
||||
case 0:
|
||||
case 1:
|
||||
printk_info("82945G");
|
||||
break;
|
||||
case 2:
|
||||
printk_info("82945G/GZ/GC");
|
||||
break;
|
||||
case 0x80:
|
||||
case 0x81:
|
||||
case 0x82:
|
||||
printk_info("82945P/PL");
|
||||
break;
|
||||
default:
|
||||
printk_info("Unknown (%02x)", reg8); /* Others unknown. */
|
||||
}
|
||||
printk_info(" Chipset\n");
|
||||
|
||||
printk_debug("(G)MCH capable of ");
|
||||
reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
|
||||
switch (reg8) {
|
||||
case 0:
|
||||
printk_debug("up to DDR2-667");
|
||||
break;
|
||||
case 3:
|
||||
printk_debug("up to DDR2-533");
|
||||
break;
|
||||
default:
|
||||
printk_info("unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
|
||||
}
|
||||
printk_debug("\n");
|
||||
}
|
||||
|
||||
static void i945_setup_bars(void)
|
||||
{
|
||||
u8 reg8;
|
||||
|
|
@ -343,6 +382,7 @@ static void i945_setup_dmi_rcrb(void)
|
|||
reg32 |= (2 << 12);
|
||||
|
||||
reg32 &= ~(7 << 15);
|
||||
|
||||
reg32 |= (2 << 15);
|
||||
DMIBAR32(DMILCAP) = reg32;
|
||||
|
||||
|
|
@ -350,7 +390,6 @@ static void i945_setup_dmi_rcrb(void)
|
|||
reg32 &= 0x00ffffff;
|
||||
reg32 &= ~(3 << 0);
|
||||
reg32 |= (1 << 0);
|
||||
|
||||
reg32 &= ~(3 << 20);
|
||||
reg32 |= (1 << 20);
|
||||
|
||||
|
|
@ -379,8 +418,10 @@ static void i945_setup_dmi_rcrb(void)
|
|||
DMIBAR32(0x204) = reg32;
|
||||
|
||||
if (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x54) & ((1 << 4) | (1 << 3))) { /* DEVEN */
|
||||
printk_debug("Internal graphics: enabled\n");
|
||||
DMIBAR32(0x200) |= (1 << 21);
|
||||
} else {
|
||||
printk_debug("Internal graphics: disabled\n");
|
||||
DMIBAR32(0x200) &= ~(1 << 21);
|
||||
}
|
||||
|
||||
|
|
@ -449,9 +490,10 @@ static void i945_setup_dmi_rcrb(void)
|
|||
if ((MCHBAR32(0x214) & 0xf) != 0x3) {
|
||||
printk_info
|
||||
("DMI link requires A1 stepping workaround. Rebooting.\n");
|
||||
reg32 = MCHBAR32(MMARB1);
|
||||
reg32 &= 0xfffffff8;
|
||||
reg32 |= 3;
|
||||
reg32 = DMIBAR32(0x224);
|
||||
reg32 &= ~(7 << 0);
|
||||
reg32 |= (3 << 0);
|
||||
DMIBAR32(0x224) = reg32;
|
||||
outb(0x06, 0xcf9);
|
||||
for (;;) ; /* wait for reset */
|
||||
}
|
||||
|
|
@ -463,7 +505,7 @@ static void i945_setup_pci_express_x16(void)
|
|||
u32 timeout;
|
||||
u32 reg32;
|
||||
u16 reg16;
|
||||
#if SETUP_PCIE_X16_LINK
|
||||
|
||||
u8 reg8;
|
||||
|
||||
printk_debug("Enabling PCI Express x16 Link\n");
|
||||
|
|
@ -476,6 +518,10 @@ static void i945_setup_pci_express_x16(void)
|
|||
reg32 &= ~(1 << 8);
|
||||
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32);
|
||||
|
||||
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
|
||||
reg32 &= ~(1 << 8);
|
||||
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
|
||||
|
||||
MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) );
|
||||
|
||||
/* Initialze PEG_CAP */
|
||||
|
|
@ -489,13 +535,15 @@ static void i945_setup_pci_express_x16(void)
|
|||
*/
|
||||
/* NOTE: SLOTCAP becomes RO after the first write! */
|
||||
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xb4);
|
||||
reg32 &= 0x0007ffff; // TODO
|
||||
reg32 &= 0xfffe007f; // TODO
|
||||
reg32 &= 0x0007ffff;
|
||||
|
||||
reg32 &= 0xfffe007f;
|
||||
|
||||
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32);
|
||||
|
||||
/* Wait for training to succeed */
|
||||
printk_debug("Wait for PCIe x16 link training ...");
|
||||
timeout = 0x7fffff;
|
||||
timeout = 0x7fff;
|
||||
while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
|
||||
if (!timeout) {
|
||||
printk_debug("timeout!\n");
|
||||
|
|
@ -515,7 +563,7 @@ static void i945_setup_pci_express_x16(void)
|
|||
pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
|
||||
|
||||
printk_debug("Wait for PCIe x1 link training ...");
|
||||
timeout = 0x7fffff;
|
||||
timeout = 0x7fff;
|
||||
while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
|
||||
if (!timeout) {
|
||||
printk_debug("timeout!\n");
|
||||
|
|
@ -531,11 +579,11 @@ static void i945_setup_pci_express_x16(void)
|
|||
reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xb2);
|
||||
reg16 >>= 4;
|
||||
reg16 &= 0x3f;
|
||||
|
||||
/* reg16 == 1 -> x1; reg16 == 16 -> x16 */
|
||||
printk_debug("PCIe x%d link training succeeded.\n", reg16);
|
||||
|
||||
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x204);
|
||||
reg32 &= 0xfffffc00;
|
||||
reg32 &= 0xfffffc00; /* clear [9:0] */
|
||||
if (reg16 == 1) {
|
||||
reg32 |= 0x32b;
|
||||
// TODO
|
||||
|
|
@ -597,6 +645,10 @@ static void i945_setup_pci_express_x16(void)
|
|||
reg32 |= (3 << 24);
|
||||
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
|
||||
|
||||
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xf0);
|
||||
reg32 |= (1 << 5);
|
||||
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
|
||||
|
||||
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x200);
|
||||
reg32 &= ~(3 << 26);
|
||||
reg32 |= (2 << 26);
|
||||
|
|
@ -647,7 +699,6 @@ static void i945_setup_pci_express_x16(void)
|
|||
return;
|
||||
|
||||
disable_pciexpress_x16_link:
|
||||
#endif
|
||||
/* For now we just disable the x16 link */
|
||||
printk_debug("Disabling PCI Express x16 Link\n");
|
||||
|
||||
|
|
@ -750,7 +801,15 @@ static void ich7_setup_pci_express(void)
|
|||
static void i945_early_initialization(void)
|
||||
{
|
||||
/* Print some chipset specific information */
|
||||
switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) {
|
||||
case 0x27708086:
|
||||
i945_detect_chipset();
|
||||
break;
|
||||
case 0x27a08086:
|
||||
case 0x27ac8086:
|
||||
i945m_detect_chipset();
|
||||
break;
|
||||
}
|
||||
|
||||
/* Setup all BARs required for early PCIe and raminit */
|
||||
i945_setup_bars();
|
||||
|
|
@ -778,3 +837,4 @@ static void i945_late_initialization(void)
|
|||
|
||||
i945_setup_root_complex_topology();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
#ifndef __NORTHBRIDGE_INTEL_I945_I945_H__
|
||||
#define __NORTHBRIDGE_INTEL_I945_I945_H__ 1
|
||||
|
||||
#include "ich7.h"
|
||||
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
|
||||
|
||||
/* Device 0:0.0 PCI configuration space (Host Bridge) */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,142 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __NORTHBRIDGE_INTEL_I945_ICH7_H__
|
||||
#define __NORTHBRIDGE_INTEL_I945_ICH7_H__ 1
|
||||
|
||||
/* Southbridge IO BARs */
|
||||
/* TODO Make sure these don't get changed by stage2 */
|
||||
#define GPIOBASE 0x48
|
||||
#define DEFAULT_GPIOBASE 0x480
|
||||
|
||||
#define PMBASE 0x40
|
||||
#define DEFAULT_PMBASE 0x500
|
||||
|
||||
/* Root Complex Register Block */
|
||||
#define RCBA 0xf0
|
||||
#define DEFAULT_RCBA 0xfed1c000
|
||||
|
||||
#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
|
||||
#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
|
||||
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
|
||||
|
||||
#define VCH 0x0000 /* 32bit */
|
||||
#define VCAP1 0x0004 /* 32bit */
|
||||
#define VCAP2 0x0008 /* 32bit */
|
||||
#define PVC 0x000c /* 16bit */
|
||||
#define PVS 0x000e /* 16bit */
|
||||
|
||||
#define V0CAP 0x0010 /* 32bit */
|
||||
#define V0CTL 0x0014 /* 32bit */
|
||||
#define V0STS 0x001a /* 16bit */
|
||||
|
||||
#define V1CAP 0x001c /* 32bit */
|
||||
#define V1CTL 0x0020 /* 32bit */
|
||||
#define V1STS 0x0026 /* 16bit */
|
||||
|
||||
#define RCTCL 0x0100 /* 32bit */
|
||||
#define ESD 0x0104 /* 32bit */
|
||||
#define ULD 0x0110 /* 32bit */
|
||||
#define ULBA 0x0118 /* 64bit */
|
||||
|
||||
#define RP1D 0x0120 /* 32bit */
|
||||
#define RP1BA 0x0128 /* 64bit */
|
||||
#define RP2D 0x0130 /* 32bit */
|
||||
#define RP2BA 0x0138 /* 64bit */
|
||||
#define RP3D 0x0140 /* 32bit */
|
||||
#define RP3BA 0x0148 /* 64bit */
|
||||
#define RP4D 0x0150 /* 32bit */
|
||||
#define RP4BA 0x0158 /* 64bit */
|
||||
#define HDD 0x0160 /* 32bit */
|
||||
#define HDBA 0x0168 /* 64bit */
|
||||
#define RP5D 0x0170 /* 32bit */
|
||||
#define RP5BA 0x0178 /* 64bit */
|
||||
#define RP6D 0x0180 /* 32bit */
|
||||
#define RP6BA 0x0188 /* 64bit */
|
||||
|
||||
#define ILCL 0x01a0 /* 32bit */
|
||||
#define LCAP 0x01a4 /* 32bit */
|
||||
#define LCTL 0x01a8 /* 16bit */
|
||||
#define LSTS 0x01aa /* 16bit */
|
||||
|
||||
#define RPC 0x0224 /* 32bit */
|
||||
#define RPFN 0x0238 /* 32bit */
|
||||
|
||||
#define TRSR 0x1e00 /* 8bit */
|
||||
#define TRCR 0x1e10 /* 64bit */
|
||||
#define TWDR 0x1e18 /* 64bit */
|
||||
|
||||
#define IOTR0 0x1e80 /* 64bit */
|
||||
#define IOTR1 0x1e88 /* 64bit */
|
||||
#define IOTR2 0x1e90 /* 64bit */
|
||||
#define IOTR3 0x1e98 /* 64bit */
|
||||
|
||||
#define TCTL 0x3000 /* 8bit */
|
||||
|
||||
#define D31IP 0x3100 /* 32bit */
|
||||
#define D30IP 0x3104 /* 32bit */
|
||||
#define D29IP 0x3108 /* 32bit */
|
||||
#define D28IP 0x310c /* 32bit */
|
||||
#define D27IP 0x3110 /* 32bit */
|
||||
#define D31IR 0x3140 /* 16bit */
|
||||
#define D30IR 0x3142 /* 16bit */
|
||||
#define D29IR 0x3144 /* 16bit */
|
||||
#define D28IR 0x3146 /* 16bit */
|
||||
#define D27IR 0x3148 /* 16bit */
|
||||
#define OIC 0x31ff /* 8bit */
|
||||
|
||||
#define RC 0x3400 /* 32bit */
|
||||
#define HPTC 0x3404 /* 32bit */
|
||||
#define GCS 0x3410 /* 32bit */
|
||||
#define BUC 0x3414 /* 32bit */
|
||||
#define FD 0x3418 /* 32bit */
|
||||
#define CG 0x341c /* 32bit */
|
||||
|
||||
/* Function Disable (FD) register values.
|
||||
* Setting a bit disables the corresponding
|
||||
* feature.
|
||||
* Not all features might be disabled on
|
||||
* all chipsets. Esp. ICH-7U is picky.
|
||||
*/
|
||||
#define FD_PCIE6 (1 << 21)
|
||||
#define FD_PCIE5 (1 << 20)
|
||||
#define FD_PCIE4 (1 << 19)
|
||||
#define FD_PCIE3 (1 << 18)
|
||||
#define FD_PCIE2 (1 << 17)
|
||||
#define FD_PCIE1 (1 << 16)
|
||||
#define FD_EHCI (1 << 15)
|
||||
#define FD_LPCB (1 << 14)
|
||||
|
||||
/* UHCI must be disabled from 4 downwards.
|
||||
* If UHCI controllers get disabled, EHCI
|
||||
* must know about it, too! */
|
||||
#define FD_UHCI4 (1 << 11)
|
||||
#define FD_UHCI34 (1 << 10) | FD_UHCI4
|
||||
#define FD_UHCI234 (1 << 9) | FD_UHCI3
|
||||
#define FD_UHCI1234 (1 << 8) | FD_UHCI2
|
||||
|
||||
#define FD_INTLAN (1 << 7)
|
||||
#define FD_ACMOD (1 << 6)
|
||||
#define FD_ACAUD (1 << 5)
|
||||
#define FD_HDAUD (1 << 4)
|
||||
#define FD_SMBUS (1 << 3)
|
||||
#define FD_SATA (1 << 2)
|
||||
#define FD_PATA (1 << 1)
|
||||
|
||||
#endif
|
||||
|
|
@ -28,9 +28,67 @@
|
|||
#include <string.h>
|
||||
#include <bitops.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <boot/tables.h>
|
||||
#include "chip.h"
|
||||
#include "i945.h"
|
||||
|
||||
int get_pcie_bar(u32 *base, u32 *len)
|
||||
{
|
||||
device_t dev;
|
||||
u32 pciexbar_reg;
|
||||
|
||||
*base = 0;
|
||||
*len = 0;
|
||||
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
|
||||
if (!dev)
|
||||
return 0;
|
||||
|
||||
pciexbar_reg = pci_read_config32(dev, 0x48);
|
||||
|
||||
if (!(pciexbar_reg & (1 << 0)))
|
||||
return 0;
|
||||
|
||||
switch ((pciexbar_reg >> 1) & 3) {
|
||||
case 0: // 256MB
|
||||
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
|
||||
*len = 256 * 1024 * 1024;
|
||||
return 1;
|
||||
case 1: // 128M
|
||||
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
|
||||
*len = 128 * 1024 * 1024;
|
||||
return 1;
|
||||
case 2: // 64M
|
||||
*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
|
||||
*len = 64 * 1024 * 1024;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* in arch/i386/boot/tables.c */
|
||||
extern uint64_t high_tables_base, high_tables_size;
|
||||
|
||||
/* IDG memory */
|
||||
uint64_t uma_memory_base=0, uma_memory_size=0;
|
||||
|
||||
int add_northbridge_resources(struct lb_memory *mem)
|
||||
{
|
||||
u32 pcie_config_base, pcie_config_size;
|
||||
|
||||
printk_debug("Adding UMA memory area\n");
|
||||
lb_add_memory_range(mem, LB_MEM_RESERVED,
|
||||
uma_memory_base, uma_memory_size);
|
||||
|
||||
printk_debug("Adding PCIe config bar\n");
|
||||
get_pcie_bar(&pcie_config_base, &pcie_config_size);
|
||||
lb_add_memory_range(mem, LB_MEM_RESERVED,
|
||||
pcie_config_base, pcie_config_size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ram_resource(device_t dev, unsigned long index, unsigned long basek,
|
||||
unsigned long sizek)
|
||||
{
|
||||
|
|
@ -72,7 +130,6 @@ static uint32_t find_pci_tolm(struct bus *bus)
|
|||
#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
|
||||
extern uint64_t high_tables_base, high_tables_size;
|
||||
#endif
|
||||
uint64_t uma_memory_base=0, uma_memory_size=0;
|
||||
|
||||
static void pci_domain_set_resources(device_t dev)
|
||||
{
|
||||
|
|
@ -81,7 +138,11 @@ static void pci_domain_set_resources(device_t dev)
|
|||
uint16_t reg16;
|
||||
unsigned long long tomk;
|
||||
|
||||
/* Can we find out how much memory we can use at most
|
||||
* this way?
|
||||
*/
|
||||
pci_tolm = find_pci_tolm(&dev->link[0]);
|
||||
printk_debug("pci_tolm: 0x%x\n", pci_tolm);
|
||||
|
||||
printk_spew("Base of stolen memory: 0x%08x\n",
|
||||
pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
|
||||
|
|
@ -200,10 +261,9 @@ static void mc_read_resources(device_t dev)
|
|||
|
||||
static void mc_set_resources(device_t dev)
|
||||
{
|
||||
struct resource *resource, *last;
|
||||
struct resource *resource;
|
||||
|
||||
/* Report the PCIe BAR */
|
||||
last = &dev->resource[dev->resources];
|
||||
resource = find_resource(dev, 0xcf);
|
||||
if (resource) {
|
||||
report_resource_stored(dev, resource, "<mmconfig>");
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
@ -17,7 +17,6 @@
|
|||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <cpu/x86/mem.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
|
|
@ -34,7 +33,6 @@
|
|||
#define PRINTK_DEBUG(x...)
|
||||
#endif
|
||||
|
||||
|
||||
#define RAM_INITIALIZATION_COMPLETE (1 << 19)
|
||||
|
||||
#define RAM_COMMAND_SELF_REFRESH (0x0 << 16)
|
||||
|
|
@ -68,7 +66,6 @@ static void do_ram_command(u32 command)
|
|||
PRINTK_DEBUG("...done\n");
|
||||
}
|
||||
|
||||
|
||||
static void ram_read32(u32 offset)
|
||||
{
|
||||
PRINTK_DEBUG(" ram read: %08x\n", offset);
|
||||
|
|
@ -94,6 +91,10 @@ static int sdram_capabilities_max_supported_memory_frequency(void)
|
|||
{
|
||||
u32 reg32;
|
||||
|
||||
#ifdef MAXIMUM_SUPPORTED_FREQUENCY
|
||||
return MAXIMUM_SUPPORTED_FREQUENCY;
|
||||
#endif
|
||||
|
||||
reg32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4);
|
||||
reg32 &= (7 << 0);
|
||||
|
||||
|
|
@ -171,9 +172,26 @@ static int sdram_capabilities_MEM4G_disable(void)
|
|||
return (reg8 != 0);
|
||||
}
|
||||
|
||||
#define GFX_FREQUENCY_CAP_166MHZ 0x04
|
||||
#define GFX_FREQUENCY_CAP_200MHZ 0x03
|
||||
#define GFX_FREQUENCY_CAP_250MHZ 0x02
|
||||
#define GFX_FREQUENCY_CAP_ALL 0x00
|
||||
|
||||
static int sdram_capabilities_core_frequencies(void)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); /* CAPID0 + 5 */
|
||||
reg8 &= (1 << 3) | (1 << 2) | (1 << 1);
|
||||
reg8 >>= 1;
|
||||
|
||||
return (reg8);
|
||||
}
|
||||
|
||||
static void sdram_detect_errors(void)
|
||||
{
|
||||
u8 reg8;
|
||||
u8 do_reset = 0;
|
||||
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
|
||||
|
||||
|
|
@ -182,12 +200,14 @@ static void sdram_detect_errors(void)
|
|||
printk_debug("SLP S4# Assertion Width Violation.\n");
|
||||
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
|
||||
|
||||
}
|
||||
|
||||
if (reg8 & (1<<7)) {
|
||||
printk_debug("DRAM initialization was interrupted.\n");
|
||||
reg8 &= ~(1<<7);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
|
||||
do_reset = 1;
|
||||
}
|
||||
|
||||
/* Set SLP_S3# Assertion Stretch Enable */
|
||||
|
|
@ -195,11 +215,13 @@ static void sdram_detect_errors(void)
|
|||
reg8 |= (1 << 3);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
|
||||
|
||||
if (do_reset) {
|
||||
printk_debug("Reset required.\n");
|
||||
outb(0x00, 0xcf9);
|
||||
outb(0x0e, 0xcf9);
|
||||
for (;;) ; /* Wait for reset! */
|
||||
}
|
||||
}
|
||||
|
||||
/* Set DRAM initialization bit in ICH7 */
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
|
||||
|
|
@ -208,7 +230,6 @@ static void sdram_detect_errors(void)
|
|||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get generic DIMM parameters.
|
||||
* @param sysinfo Central memory controller information structure
|
||||
|
|
@ -272,8 +293,11 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
|
|||
/* Initialize the socket information with a sane value */
|
||||
sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
|
||||
|
||||
/* Dual Channel not supported, but Channel 1? Bail out */
|
||||
if (!sdram_capabilities_dual_channel() && (i >> 1))
|
||||
continue;
|
||||
|
||||
/* Two DIMMs per channel not supported, but odd DIMM number? */
|
||||
if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
|
||||
continue;
|
||||
|
||||
|
|
@ -596,7 +620,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
|
|||
case 667: freq_multiplier = 0x0c; break; /* 3ns */
|
||||
}
|
||||
|
||||
tRCD_cycles = 2;
|
||||
tRCD_cycles = 2; /* 2 clocks minimum */
|
||||
tRCD_time = tRCD_cycles * freq_multiplier;
|
||||
|
||||
for (i=0; i<2*DIMM_SOCKETS; i++) {
|
||||
|
|
@ -705,8 +729,8 @@ static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
|
|||
}
|
||||
index--;
|
||||
switch (sysinfo->memory_frequency) {
|
||||
case 667: index += 3;
|
||||
case 533: index += 3;
|
||||
case 667: index += 3; /* Fallthrough */
|
||||
case 533: index += 3; /* Fallthrough */
|
||||
case 400: break;
|
||||
}
|
||||
|
||||
|
|
@ -714,7 +738,6 @@ static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
|
|||
printk_debug("tRFC = %d cycles\n", tRFC_cycles[index]);
|
||||
}
|
||||
|
||||
|
||||
static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -823,7 +846,6 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
|
|||
static const u32 cmd2710[] = {
|
||||
0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
|
||||
0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f,
|
||||
|
||||
0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b,
|
||||
0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f
|
||||
};
|
||||
|
|
@ -925,7 +947,6 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
|
|||
dq2330, nc, ctl3215, nc, clk2030, clk2030, dq2030, cmd3210
|
||||
};
|
||||
|
||||
|
||||
/* Strength multiplier tables */
|
||||
static const u8 dual_channel_strength_multiplier[] = {
|
||||
0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11,
|
||||
|
|
@ -1016,7 +1037,6 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
|
|||
sdram_write_slew_rates(G2SRPUT, slew_group_lookup[idx * 8 + 1]);
|
||||
if ((slew_group_lookup[idx * 8 + 2] != nc) && (sysinfo->package == SYSINFO_PACKAGE_STACKED)) {
|
||||
|
||||
|
||||
sdram_write_slew_rates(G3SRPUT, ctl3220);
|
||||
} else {
|
||||
sdram_write_slew_rates(G3SRPUT, slew_group_lookup[idx * 8 + 2]);
|
||||
|
|
@ -1038,7 +1058,7 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
|
|||
static void sdram_enable_rcomp(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
/* Enable Global Periodic RCOMP */
|
||||
udelay(300);
|
||||
reg32 = MCHBAR32(GBRCOMPCTL);
|
||||
reg32 &= ~(1 << 23);
|
||||
|
|
@ -1083,6 +1103,7 @@ static void sdram_force_rcomp(void)
|
|||
reg32 |= (1 << 0);
|
||||
MCHBAR32(SMSRCTL) = reg32;
|
||||
|
||||
/* Start initial RCOMP */
|
||||
reg32 = MCHBAR32(GBRCOMPCTL);
|
||||
reg32 |= (1 << 8);
|
||||
MCHBAR32(GBRCOMPCTL) = reg32;
|
||||
|
|
@ -1101,7 +1122,7 @@ static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
|
|||
u32 reg32;
|
||||
|
||||
printk_debug ("Initializing System Memory IO... \n");
|
||||
|
||||
/* Enable Data Half Clock Pushout */
|
||||
reg8 = MCHBAR8(C0HCTC);
|
||||
reg8 &= ~0x1f;
|
||||
reg8 |= ( 1 << 0);
|
||||
|
|
@ -1112,17 +1133,18 @@ static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
|
|||
reg8 |= ( 1 << 0);
|
||||
MCHBAR8(C1HCTC) = reg8;
|
||||
|
||||
|
||||
MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) );
|
||||
MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0);
|
||||
|
||||
MCHBAR8(C0WDLLCMC) = 0;
|
||||
MCHBAR8(C1WDLLCMC) = 0;
|
||||
|
||||
/* Program RCOMP Settings */
|
||||
sdram_program_dram_width(sysinfo);
|
||||
|
||||
sdram_rcomp_buffer_strength_and_slew(sysinfo);
|
||||
|
||||
/* Indicate that RCOMP programming is done */
|
||||
reg32 = MCHBAR32(GBRCOMPCTL);
|
||||
reg32 &= ~( (1 << 29) | (1 << 26) | (3 << 21) | (3 << 2) );
|
||||
reg32 |= (3 << 27) | (3 << 0);
|
||||
|
|
@ -1130,8 +1152,10 @@ static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
|
|||
|
||||
MCHBAR32(GBRCOMPCTL) |= (1 << 10);
|
||||
|
||||
/* Program DLL Timings */
|
||||
sdram_program_dll_timings(sysinfo);
|
||||
|
||||
/* Force RCOMP cycle */
|
||||
sdram_force_rcomp();
|
||||
}
|
||||
|
||||
|
|
@ -1143,7 +1167,7 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
|
|||
|
||||
reg32 = MCHBAR32(RCVENMT);
|
||||
reg32 &= ~(0x3f << 6);
|
||||
MCHBAR32(RCVENMT) = reg32;
|
||||
MCHBAR32(RCVENMT) = reg32; /* [11:6] = 0 */
|
||||
|
||||
reg32 |= (1 << 11) | (1 << 9);
|
||||
MCHBAR32(RCVENMT) = reg32;
|
||||
|
|
@ -1176,6 +1200,7 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
|
|||
|
||||
MCHBAR32(DRTST) = reg32;
|
||||
|
||||
/* Activate DRAM Channel IO Buffers */
|
||||
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED ||
|
||||
sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) {
|
||||
reg32 = MCHBAR32(C0DRC1);
|
||||
|
|
@ -1290,9 +1315,9 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
|
|||
if (sz.side1 < 30)
|
||||
die("DDR-II rank size smaller than 128MB is not supported.\n");
|
||||
|
||||
sysinfo->banksize[i * 2] = sz.side1 - 30;
|
||||
sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
|
||||
|
||||
printk_debug("DIMM %d side 0 = %d MB\n", i, (1 << sysinfo->banksize[i * 2]) * 128 );
|
||||
printk_debug("DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
|
||||
|
||||
if (!sz.side2)
|
||||
continue;
|
||||
|
|
@ -1301,22 +1326,22 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
|
|||
if (sz.side2 < 30)
|
||||
die("DDR-II rank size smaller than 128MB is not supported.\n");
|
||||
|
||||
sysinfo->banksize[(i * 2) + 1] = sz.side2 - 30;
|
||||
sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
|
||||
|
||||
printk_debug("DIMM %d side 1 = %d MB\n", i, (1 << sysinfo->banksize[(i * 2) + 1]) * 128);
|
||||
printk_debug("DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
|
||||
}
|
||||
}
|
||||
|
||||
static int sdram_program_row_boundaries(struct sys_info *sysinfo)
|
||||
{
|
||||
int i;
|
||||
int cum0, cum1, tolud;
|
||||
int cum0, cum1, tolud, tom;
|
||||
|
||||
printk_debug ("Setting RAM size... \n");
|
||||
|
||||
cum0 = 0;
|
||||
for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
|
||||
cum0 += (sysinfo->banksize[i] << 3);
|
||||
cum0 += sysinfo->banksize[i];
|
||||
MCHBAR8(C0DRB0+i) = cum0;
|
||||
}
|
||||
|
||||
|
|
@ -1333,7 +1358,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
|
|||
cum1 = 0;
|
||||
|
||||
for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
|
||||
cum1 += (sysinfo->banksize[i + 4] << 3);
|
||||
cum1 += sysinfo->banksize[i + 4];
|
||||
MCHBAR8(C1DRB0+i) = cum1;
|
||||
}
|
||||
|
||||
|
|
@ -1343,21 +1368,24 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
|
|||
else
|
||||
tolud = (cum1 ? cum1 : cum0) << 1;
|
||||
|
||||
/* Some extra checks needed. See 4.1.26 in the
|
||||
* 82945G MCH datasheet (30750203)
|
||||
*/
|
||||
pci_write_config16(PCI_DEV(0,0,0), TOLUD, tolud);
|
||||
/* The TOM register has a different format */
|
||||
tom = tolud >> 3;
|
||||
|
||||
/* Limit the value of TOLUD to leave some space for PCI memory. */
|
||||
if (tolud > 0xd0)
|
||||
tolud = 0xd0; /* 3.25GB : 0.75GB */
|
||||
|
||||
pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
|
||||
|
||||
printk_debug("C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
|
||||
printk_debug("C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
|
||||
printk_debug("TOLUD = 0x%04x\n", tolud);
|
||||
printk_debug("TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
|
||||
|
||||
pci_write_config16(PCI_DEV(0,0,0), TOM, tolud>>3);
|
||||
pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int sdram_set_row_attributes(struct sys_info *sysinfo)
|
||||
{
|
||||
int i, value;
|
||||
|
|
@ -1373,7 +1401,6 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
|
|||
}
|
||||
|
||||
device = DIMM_SPD_BASE + i;
|
||||
columnsrows = 0;
|
||||
|
||||
value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */
|
||||
columnsrows = (value & 0x0f);
|
||||
|
|
@ -1578,7 +1605,7 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo)
|
|||
reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR;
|
||||
temp_drt |= (reg32 << 24);
|
||||
|
||||
|
||||
/* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
|
||||
temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );
|
||||
|
||||
/* Program Write Auto Precharge to Activate */
|
||||
|
|
@ -1703,7 +1730,6 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo)
|
|||
( sysinfo->banksize[4] + sysinfo->banksize[5] +
|
||||
sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) {
|
||||
/* Both channels equipped with DIMMs of the same size */
|
||||
|
||||
sysinfo->interleaved = 1;
|
||||
} else {
|
||||
sysinfo->interleaved = 0;
|
||||
|
|
@ -1738,39 +1764,37 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo)
|
|||
PRINTK_DEBUG("DCC=0x%08x\n", MCHBAR32(DCC));
|
||||
}
|
||||
|
||||
static void sdram_program_pll_settings(void)
|
||||
static void sdram_program_pll_settings(struct sys_info *sysinfo)
|
||||
{
|
||||
volatile u16 reg16;
|
||||
volatile u32 reg32;
|
||||
|
||||
const u8 HPLLGPLLPowerDown[] = {
|
||||
0x90, /* 400MHz */
|
||||
0x95, /* 533MHz */
|
||||
0x00, /* --- */
|
||||
0x8d, /* 667MHz */
|
||||
};
|
||||
|
||||
MCHBAR32(PLLMON) = 0x80800000;
|
||||
|
||||
reg32 = MCHBAR32(CLKCFG);
|
||||
reg32 &= (7 << 0);
|
||||
switch (MCHBAR32(CLKCFG) & 0x7) {
|
||||
case 0: sysinfo->fsb_frequency = 400; break; /* FSB400 */
|
||||
case 1: sysinfo->fsb_frequency = 533; break; /* FSB533 */
|
||||
case 3: sysinfo->fsb_frequency = 667; break; /* FSB667 */
|
||||
default: die("Unsupported FSB speed");
|
||||
}
|
||||
|
||||
reg16 = MCHBAR16(CPCTL);
|
||||
reg16 &= 0xff00;
|
||||
reg16 |= HPLLGPLLPowerDown[reg32];
|
||||
MCHBAR16(CPCTL) = reg16;
|
||||
/* Program CPCTL according to FSB speed */
|
||||
/* Only write the lower byte */
|
||||
switch (sysinfo->fsb_frequency) {
|
||||
case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */
|
||||
case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */
|
||||
case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */
|
||||
}
|
||||
|
||||
reg16 &= ~(1 << 11);
|
||||
MCHBAR16(CPCTL) = reg16;
|
||||
MCHBAR16(CPCTL) &= ~(1 << 11);
|
||||
|
||||
reg16 = MCHBAR16(CPCTL);
|
||||
reg16 = MCHBAR16(CPCTL); /* Read back register to activate settings */
|
||||
}
|
||||
|
||||
static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
|
||||
{
|
||||
u8 reg8;
|
||||
u16 reg16;
|
||||
u8 freq, second_vco;
|
||||
u8 freq, second_vco, voltage;
|
||||
|
||||
#define CRCLK_166MHz 0x00
|
||||
#define CRCLK_200MHz 0x01
|
||||
|
|
@ -1780,62 +1804,63 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
|
|||
#define CDCLK_200MHz 0x00
|
||||
#define CDCLK_320MHz 0x40
|
||||
|
||||
#define VOLTAGE_1_05 0x00
|
||||
#define VOLTAGE_1_50 0x01
|
||||
|
||||
printk_debug ("Setting Graphics Frequency... \n");
|
||||
|
||||
reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
|
||||
reg16 |= (1<<11) | (1<<9);
|
||||
pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
|
||||
printk_debug("FSB: %d MHz ", sysinfo->fsb_frequency);
|
||||
|
||||
/* Program CPCTL according to FSB speed */
|
||||
reg16 = MCHBAR16(CPCTL);
|
||||
reg16 &= 0xff00;
|
||||
voltage = VOLTAGE_1_05;
|
||||
if (MCHBAR32(DFT_STRAP1) & (1 << 20))
|
||||
voltage = VOLTAGE_1_50;
|
||||
printk_debug("Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
|
||||
|
||||
switch (MCHBAR32(CLKCFG) & 0x7) {
|
||||
case 0: sysinfo->fsb_frequency = 400; break; /* FSB400 */
|
||||
case 1: sysinfo->fsb_frequency = 533; break; /* FSB533 */
|
||||
case 3: sysinfo->fsb_frequency = 667; break; /* FSB667 */
|
||||
default: die("Unsupported FSB speed");
|
||||
}
|
||||
|
||||
switch (sysinfo->fsb_frequency) {
|
||||
case 533: reg16 |= 0x95; break; /* FSB533 */
|
||||
case 667: reg16 |= 0x8d; break; /* FSB667 */
|
||||
}
|
||||
MCHBAR16(CPCTL) = reg16;
|
||||
/* Gate graphics hardware for frequency change */
|
||||
reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
|
||||
reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */
|
||||
pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
|
||||
|
||||
/* Get graphics frequency capabilities */
|
||||
reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe5) & 0x0e) >> 1;
|
||||
reg8 = sdram_capabilities_core_frequencies();
|
||||
|
||||
freq = CRCLK_250MHz;
|
||||
switch (reg8) {
|
||||
case 0:
|
||||
if (MCHBAR32(DFT_STRAP1) & (1 << 20))
|
||||
case GFX_FREQUENCY_CAP_ALL:
|
||||
if (voltage == VOLTAGE_1_05)
|
||||
freq = CRCLK_250MHz;
|
||||
else
|
||||
freq = CRCLK_400MHz;
|
||||
break;
|
||||
case 2: freq = CRCLK_250MHz; break;
|
||||
case 3: freq = CRCLK_200MHz; break;
|
||||
case 4: freq = CRCLK_166MHz; break;
|
||||
case GFX_FREQUENCY_CAP_250MHZ: freq = CRCLK_250MHz; break;
|
||||
case GFX_FREQUENCY_CAP_200MHZ: freq = CRCLK_200MHz; break;
|
||||
case GFX_FREQUENCY_CAP_166MHZ: freq = CRCLK_166MHz; break;
|
||||
}
|
||||
|
||||
if (freq != CRCLK_400MHz) {
|
||||
|
||||
/* What chipset are we? Force 166MHz for GMS */
|
||||
reg8 = (pci_read_config8(PCI_DEV(0, 0x00,0), 0xe7) & 0x70) >> 4;
|
||||
if (reg8==2)
|
||||
freq = CRCLK_166MHz;
|
||||
}
|
||||
|
||||
printk_debug("Render: ");
|
||||
switch (freq) {
|
||||
case CRCLK_166MHz: printk_debug("166Mhz"); break;
|
||||
case CRCLK_200MHz: printk_debug("200Mhz"); break;
|
||||
case CRCLK_250MHz: printk_debug("250Mhz"); break;
|
||||
case CRCLK_400MHz: printk_debug("400Mhz"); break;
|
||||
}
|
||||
|
||||
if (i945_silicon_revision() == 0) {
|
||||
sysinfo->mvco4x = 1;
|
||||
} else {
|
||||
sysinfo->mvco4x = 0;
|
||||
}
|
||||
|
||||
|
||||
second_vco = 0;
|
||||
|
||||
if (MCHBAR32(DFT_STRAP1) & (1 << 20)) {
|
||||
if (voltage == VOLTAGE_1_50) {
|
||||
second_vco = 1;
|
||||
} else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) {
|
||||
u16 mem = sysinfo->memory_frequency;
|
||||
|
|
@ -1852,34 +1877,41 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
|
|||
}
|
||||
|
||||
if (second_vco) {
|
||||
printk_debug("Programming second TCO\n");
|
||||
sysinfo->clkcfg_bit7=1;
|
||||
} else {
|
||||
sysinfo->clkcfg_bit7=0;
|
||||
}
|
||||
|
||||
/* Graphics Core Render Clock */
|
||||
reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
|
||||
reg16 &= ~( (7 << 0) | (1 << 13) );
|
||||
reg16 |= freq;
|
||||
pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
|
||||
|
||||
reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
|
||||
reg16 &= ~( (1<<7) | (7<<4) );
|
||||
if (MCHBAR32(DFT_STRAP1) & (1 << 20)) {
|
||||
reg16 |= CDCLK_200MHz;
|
||||
/* Graphics Core Display Clock */
|
||||
reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC);
|
||||
reg8 &= ~( (1<<7) | (7<<4) );
|
||||
|
||||
if (voltage == VOLTAGE_1_05) {
|
||||
reg8 |= CDCLK_200MHz;
|
||||
printk_debug(" Display: 200MHz\n");
|
||||
} else {
|
||||
reg16 |= CDCLK_320MHz;
|
||||
reg8 |= CDCLK_320MHz;
|
||||
printk_debug(" Display: 320MHz\n");
|
||||
}
|
||||
pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
|
||||
pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
|
||||
|
||||
reg16 = pci_read_config16(PCI_DEV(0,2,0), GCFC);
|
||||
reg16 &= ~( (1<<10) | (1<<8) );
|
||||
pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
|
||||
reg16 |= (1<<10) | (1<<8);
|
||||
pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
|
||||
reg8 = pci_read_config8(PCI_DEV(0,2,0), GCFC + 1);
|
||||
|
||||
reg16 &= 0xf0ff;
|
||||
pci_write_config16(PCI_DEV(0,2,0), GCFC, reg16);
|
||||
reg8 |= (1<<3) | (1<<1);
|
||||
pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
|
||||
|
||||
reg8 |= 0x0f;
|
||||
pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
|
||||
|
||||
/* Ungate core render and display clocks */
|
||||
reg8 &= 0xf0;
|
||||
pci_write_config8(PCI_DEV(0,2,0), GCFC + 1, reg8);
|
||||
}
|
||||
|
||||
static void sdram_program_memory_frequency(struct sys_info *sysinfo)
|
||||
|
|
@ -1929,13 +1961,11 @@ vco_update:
|
|||
reg8 &= ~(1 << 7);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
|
||||
|
||||
|
||||
clkcfg &= ~(1 << 10);
|
||||
MCHBAR32(CLKCFG) = clkcfg;
|
||||
clkcfg |= (1 << 10);
|
||||
MCHBAR32(CLKCFG) = clkcfg;
|
||||
|
||||
|
||||
__asm__ __volatile__ (
|
||||
" movl $0x100, %%ecx\n"
|
||||
"delay_update:\n"
|
||||
|
|
@ -1949,7 +1979,6 @@ vco_update:
|
|||
: "%ecx"
|
||||
);
|
||||
|
||||
|
||||
clkcfg &= ~(1 << 10);
|
||||
MCHBAR32(CLKCFG) = clkcfg;
|
||||
|
||||
|
|
@ -1968,12 +1997,12 @@ static void sdram_program_clock_crossing(void)
|
|||
int idx = 0;
|
||||
|
||||
/**
|
||||
* The first two lines of each of these tables are for FSB533,
|
||||
* the following three lines are for FSB667. We ignore FSB400.
|
||||
* Thus we add the indices according to our clocks from CLKCFG.
|
||||
* We add the indices according to our clocks from CLKCFG.
|
||||
*/
|
||||
|
||||
static const u32 data_clock_crossing[] = {
|
||||
0x00100401, 0x00000000, /* DDR400 FSB400 */
|
||||
|
||||
0x08040120, 0x00000000, /* DDR400 FSB533 */
|
||||
0x00100401, 0x00000000, /* DDR533 FSB533 */
|
||||
|
||||
|
|
@ -1983,6 +2012,8 @@ static void sdram_program_clock_crossing(void)
|
|||
};
|
||||
|
||||
static const u32 command_clock_crossing[] = {
|
||||
0x04020208, 0x00000000, /* DDR400 FSB400 */
|
||||
|
||||
0x00060108, 0x00000000, /* DDR400 FSB533 */
|
||||
0x04020108, 0x00000000, /* DDR533 FSB533 */
|
||||
|
||||
|
|
@ -2004,20 +2035,20 @@ static void sdram_program_clock_crossing(void)
|
|||
|
||||
printk_debug(" FSB=");
|
||||
switch (reg32 & 7) {
|
||||
case 0: printk_debug("400\n"); return;
|
||||
case 1: printk_debug("533"); idx += 0; break;
|
||||
case 3: printk_debug("667"); idx += 4; break;
|
||||
case 0: printk_debug("400\n"); idx += 0; break;
|
||||
case 1: printk_debug("533"); idx += 2; break;
|
||||
case 3: printk_debug("667"); idx += 6; break;
|
||||
default: printk_debug("RSVD\n"); return;
|
||||
}
|
||||
|
||||
MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
|
||||
MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
|
||||
|
||||
MCHBAR32(C0DCCFT + 0) = data_clock_crossing[idx];
|
||||
MCHBAR32(C0DCCFT + 4) = data_clock_crossing[idx + 1];
|
||||
MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
|
||||
MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
|
||||
|
||||
MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
|
||||
MCHBAR32(CCCFT + 4) = command_clock_crossing[idx + 1];
|
||||
|
||||
printk_debug("... ok\n");
|
||||
}
|
||||
|
||||
|
|
@ -2051,6 +2082,7 @@ static void sdram_pre_jedec_initialization(void)
|
|||
MCHBAR32(MMARB1) &= ~(7 << 8);
|
||||
MCHBAR32(MMARB1) |= (3 << 8);
|
||||
|
||||
/* Adaptive Idle Timer Control */
|
||||
MCHBAR32(C0AIT) = 0x000006c4;
|
||||
MCHBAR32(C0AIT+4) = 0x871a066d;
|
||||
|
||||
|
|
@ -2155,6 +2187,7 @@ static void sdram_post_jedec_initialization(struct sys_info *sysinfo)
|
|||
|
||||
/* Enable Channel XORing for Dual Channel Interleave */
|
||||
if (sysinfo->interleaved) {
|
||||
|
||||
reg32 = MCHBAR32(DCC);
|
||||
#if CHANNEL_XOR_RANDOMIZATION
|
||||
reg32 &= ~(1 << 10);
|
||||
|
|
@ -2213,10 +2246,16 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
MCHBAR32(C1DRC1) = reg32;
|
||||
|
||||
if (i945_silicon_revision()>1) {
|
||||
MCHBAR16(UPMC1) = 0x1010;
|
||||
/* FIXME bits 5 and 0 only if PCIe graphics is disabled */
|
||||
u16 peg_bits = (1 << 5) | (1 << 0);
|
||||
|
||||
MCHBAR16(UPMC1) = 0x1010 | peg_bits;
|
||||
} else {
|
||||
/* FIXME bits 5 and 0 only if PCIe graphics is disabled */
|
||||
u16 peg_bits = (1 << 5) | (1 << 0);
|
||||
|
||||
/* Rev 0 and 1 */
|
||||
MCHBAR16(UPMC1) = 0x0010;
|
||||
MCHBAR16(UPMC1) = 0x0010 | peg_bits;
|
||||
}
|
||||
|
||||
reg16 = MCHBAR16(UPMC2);
|
||||
|
|
@ -2243,7 +2282,6 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
MCHBAR16(CPCTL) = reg16;
|
||||
|
||||
#if 0
|
||||
/* This is set later in the game */
|
||||
if ((MCHBAR32(ECO) & (1 << 16)) != 0) {
|
||||
#else
|
||||
if (i945_silicon_revision() != 0) {
|
||||
|
|
@ -2284,6 +2322,7 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
}
|
||||
|
||||
#if 0
|
||||
|
||||
if (i945_silicon_revision() == 0) {
|
||||
MCHBAR32(FSBPMC3) &= ~(1 << 29);
|
||||
} else {
|
||||
|
|
@ -2307,8 +2346,8 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
|
||||
MCHBAR32(FSBPMC4) |= (1 << 5);
|
||||
|
||||
if (i945_silicon_revision() < 2) {
|
||||
/* stepping 0 and 1 */
|
||||
if ((i945_silicon_revision() < 2) /* || cpuid() = 0x6e8 */ ) {
|
||||
/* stepping 0 and 1 or CPUID 6e8 */
|
||||
MCHBAR32(FSBPMC4) &= ~(1 << 4);
|
||||
} else {
|
||||
MCHBAR32(FSBPMC4) |= (1 << 4);
|
||||
|
|
@ -2322,7 +2361,10 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
reg8 |= (1 << 2);
|
||||
pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8);
|
||||
|
||||
#if C2_SELF_REFRESH_DISABLE
|
||||
|
||||
if (integrated_graphics) {
|
||||
printk_debug("C2 self-refresh with IGD\n");
|
||||
MCHBAR16(MIPMC4) = 0x0468;
|
||||
MCHBAR16(MIPMC5) = 0x046c;
|
||||
MCHBAR16(MIPMC6) = 0x046c;
|
||||
|
|
@ -2331,13 +2373,26 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
MCHBAR16(MIPMC5) = 0x646c;
|
||||
MCHBAR16(MIPMC6) = 0x646c;
|
||||
}
|
||||
#else
|
||||
if (integrated_graphics) {
|
||||
MCHBAR16(MIPMC4) = 0x04f8;
|
||||
MCHBAR16(MIPMC5) = 0x04fc;
|
||||
MCHBAR16(MIPMC6) = 0x04fc;
|
||||
} else {
|
||||
MCHBAR16(MIPMC4) = 0x64f8;
|
||||
MCHBAR16(MIPMC5) = 0x64fc;
|
||||
MCHBAR16(MIPMC6) = 0x64fc;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
reg32 = MCHBAR32(PMCFG);
|
||||
reg32 &= ~(3 << 17);
|
||||
reg32 |= (2 << 17);
|
||||
reg32 |= (1 << 4);
|
||||
MCHBAR32(PMCFG) = reg32;
|
||||
|
||||
MCHBAR32(PMCFG) |= (1 << 4);
|
||||
|
||||
reg32 = MCHBAR32(0xc30);
|
||||
reg32 &= 0xffffff00;
|
||||
reg32 |= 0x01;
|
||||
|
|
@ -2348,13 +2403,76 @@ static void sdram_power_management(struct sys_info *sysinfo)
|
|||
|
||||
static void sdram_thermal_management(void)
|
||||
{
|
||||
|
||||
MCHBAR8(TCO1) = 0x00;
|
||||
MCHBAR8(TCO0) = 0x00;
|
||||
|
||||
/* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr
|
||||
* 0x30/0x32.
|
||||
*/
|
||||
|
||||
/* Explicitly set to 0 */
|
||||
MCHBAR8(TCO1) = 0x00;
|
||||
MCHBAR8(TCO0) = 0x00;
|
||||
}
|
||||
|
||||
static void sdram_save_receive_enable(void)
|
||||
{
|
||||
int i;
|
||||
u32 reg32;
|
||||
u8 values[4];
|
||||
|
||||
/* The following values are stored to an unused CMOS
|
||||
* area and restored instead of recalculated in case
|
||||
* of an S3 resume.
|
||||
*
|
||||
* C0WL0REOST [7:0] -> 8 bit
|
||||
* C1WL0REOST [7:0] -> 8 bit
|
||||
* RCVENMT [11:8] [3:0] -> 8 bit
|
||||
* C0DRT1 [27:24] -> 4 bit
|
||||
* C1DRT1 [27:24] -> 4 bit
|
||||
*/
|
||||
|
||||
values[0] = MCHBAR8(C0WL0REOST);
|
||||
values[1] = MCHBAR8(C1WL0REOST);
|
||||
|
||||
reg32 = MCHBAR32(RCVENMT);
|
||||
values[2] = (u8)((reg32 >> (8 - 4)) & 0xf0) | (reg32 & 0x0f);
|
||||
|
||||
reg32 = MCHBAR32(C0DRT1);
|
||||
values[3] = (reg32 >> 24) & 0x0f;
|
||||
reg32 = MCHBAR32(C1DRT1);
|
||||
values[3] |= (reg32 >> (24 - 4)) & 0xf0;
|
||||
|
||||
/* coreboot only uses bytes 0 - 127 for its CMOS values so far
|
||||
* so we grad bytes 128 - 131 to save the receive enable values
|
||||
*/
|
||||
|
||||
for (i=0; i<4; i++)
|
||||
cmos_write(values[i], 128 + i);
|
||||
}
|
||||
|
||||
static void sdram_recover_receive_enable(void)
|
||||
{
|
||||
int i;
|
||||
u32 reg32;
|
||||
u8 values[4];
|
||||
|
||||
for (i=0; i<4; i++)
|
||||
values[i] = cmos_read(128 + i);
|
||||
|
||||
MCHBAR8(C0WL0REOST) = values[0];
|
||||
MCHBAR8(C1WL0REOST) = values[1];
|
||||
|
||||
reg32 = MCHBAR32(RCVENMT);
|
||||
reg32 &= ~((0x0f << 8) | (0x0f << 0));
|
||||
reg32 |= ((u32)(values[2] & 0xf0) << (8 - 4)) | (values[2] & 0x0f);
|
||||
MCHBAR32(RCVENMT) = reg32;
|
||||
|
||||
reg32 = MCHBAR32(C0DRT1) & ~(0x0f << 24);
|
||||
reg32 |= (u32)(values[3] & 0x0f) << 24;
|
||||
MCHBAR32(C0DRT1) = reg32;
|
||||
|
||||
reg32 = MCHBAR32(C1DRT1) & ~(0x0f << 24);
|
||||
reg32 |= (u32)(values[3] & 0xf0) << (24 - 4);
|
||||
MCHBAR32(C1DRT1) = reg32;
|
||||
}
|
||||
|
||||
#include "rcven.c"
|
||||
|
|
@ -2363,7 +2481,13 @@ static void sdram_program_receive_enable(struct sys_info *sysinfo)
|
|||
{
|
||||
MCHBAR32(REPC) |= (1 << 0);
|
||||
|
||||
/* Program Receive Enable Timings */
|
||||
if (sysinfo->boot_path == BOOT_PATH_RESUME) {
|
||||
sdram_recover_receive_enable();
|
||||
} else {
|
||||
receive_enable_adjust(sysinfo);
|
||||
sdram_save_receive_enable();
|
||||
}
|
||||
|
||||
MCHBAR32(C0DRC1) |= (1 << 6);
|
||||
MCHBAR32(C1DRC1) |= (1 << 6);
|
||||
|
|
@ -2446,14 +2570,26 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
|
|||
clocks[1] |= (1 << 2) | (1 << 3);
|
||||
|
||||
#ifdef OVERRIDE_CLOCK_DISABLE
|
||||
clocks[0] = 0xf;
|
||||
clocks[1] = 0xf;
|
||||
/* Usually system firmware turns off system memory clock signals
|
||||
* to unused SO-DIMM slots to reduce EMI and power consumption.
|
||||
* However, the Kontron 986LCD-M does not like unused clock
|
||||
* signals to be disabled.
|
||||
* If other similar mainboard occur, it would make sense to make
|
||||
* this an entry in the sysinfo structure, and pre-initialize that
|
||||
* structure in the mainboard's auto.c main() function.
|
||||
* For now an #ifdef will do.
|
||||
*/
|
||||
|
||||
clocks[0] = 0xf; /* force all clock gate pairs to enable */
|
||||
clocks[1] = 0xf; /* force all clock gate pairs to enable */
|
||||
#endif
|
||||
|
||||
MCHBAR8(C0DCLKDIS) = clocks[0];
|
||||
MCHBAR8(C1DCLKDIS) = clocks[1];
|
||||
}
|
||||
|
||||
#define RTT_ODT_NONE 0
|
||||
#define RTT_ODT_50_OHM ( (1 << 9) | (1 << 5) )
|
||||
#define RTT_ODT_75_OHM (1 << 5)
|
||||
#define RTT_ODT_150_OHM (1 << 9)
|
||||
|
||||
|
|
@ -2496,7 +2632,8 @@ static void sdram_jedec_enable(struct sys_info *sysinfo)
|
|||
default:
|
||||
if (nonzero != -1) {
|
||||
printk_debug("bankaddr from bank size of rank %d\n", nonzero);
|
||||
bankaddr += (1 << sysinfo->banksize[nonzero]) << (sysinfo->interleaved?28:27);
|
||||
bankaddr += sysinfo->banksize[nonzero] <<
|
||||
(sysinfo->interleaved ? 26 : 25);
|
||||
break;
|
||||
}
|
||||
/* No populated bank hit before. Start at address 0 */
|
||||
|
|
@ -2524,9 +2661,11 @@ static void sdram_jedec_enable(struct sys_info *sysinfo)
|
|||
default: die("Jedec Error (tWR).\n");
|
||||
}
|
||||
|
||||
/* Set "Burst Type" */
|
||||
mrsaddr |= MRS_BT;
|
||||
|
||||
/* Interleaved */
|
||||
if (sysinfo->interleaved) {
|
||||
mrsaddr |= MRS_BT;
|
||||
mrsaddr = mrsaddr << 1;
|
||||
}
|
||||
|
||||
|
|
@ -2647,13 +2786,10 @@ static void sdram_setup_processor_side(void)
|
|||
MCHBAR32(SLPCTL) |= (1 << 8);
|
||||
}
|
||||
|
||||
#define BOOT_MODE_RESUME 1
|
||||
#define BOOT_MODE_NORMAL 0
|
||||
|
||||
/**
|
||||
* @param boot_mode: 0 = normal, 1 = resume
|
||||
* @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
|
||||
*/
|
||||
void sdram_initialize(int boot_mode)
|
||||
void sdram_initialize(int boot_path)
|
||||
{
|
||||
struct sys_info sysinfo;
|
||||
u8 reg8, cas_mask;
|
||||
|
|
@ -2664,6 +2800,8 @@ void sdram_initialize(int boot_mode)
|
|||
|
||||
memset(&sysinfo, 0, sizeof(sysinfo));
|
||||
|
||||
sysinfo.boot_path = boot_path;
|
||||
|
||||
/* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */
|
||||
sdram_get_dram_configuration(&sysinfo);
|
||||
|
||||
|
|
@ -2701,7 +2839,7 @@ void sdram_initialize(int boot_mode)
|
|||
sdram_detect_smallest_tRFC(&sysinfo);
|
||||
|
||||
/* Program PLL settings */
|
||||
sdram_program_pll_settings();
|
||||
sdram_program_pll_settings(&sysinfo);
|
||||
|
||||
/* Program Graphics Frequency */
|
||||
sdram_program_graphics_frequency(&sysinfo);
|
||||
|
|
@ -2724,13 +2862,11 @@ void sdram_initialize(int boot_mode)
|
|||
|
||||
/* Program DRAM Row Boundary/Attribute Registers */
|
||||
|
||||
if (boot_mode != BOOT_MODE_RESUME) {
|
||||
/* program row size DRB and set TOLUD */
|
||||
sdram_program_row_boundaries(&sysinfo);
|
||||
|
||||
/* program page size DRA */
|
||||
sdram_set_row_attributes(&sysinfo);
|
||||
}
|
||||
|
||||
/* Program CxBNKARC */
|
||||
sdram_set_bank_architecture(&sysinfo);
|
||||
|
|
@ -2753,7 +2889,7 @@ void sdram_initialize(int boot_mode)
|
|||
/* Enable System Memory Clocks */
|
||||
sdram_enable_memory_clocks(&sysinfo);
|
||||
|
||||
if (boot_mode != BOOT_MODE_RESUME) {
|
||||
if (boot_path == BOOT_PATH_NORMAL) {
|
||||
/* Jedec Initialization sequence */
|
||||
sdram_jedec_enable(&sysinfo);
|
||||
}
|
||||
|
|
@ -2768,7 +2904,9 @@ void sdram_initialize(int boot_mode)
|
|||
sdram_thermal_management();
|
||||
|
||||
/* Normal Operations */
|
||||
if (boot_path == BOOT_PATH_NORMAL) {
|
||||
sdram_init_complete();
|
||||
}
|
||||
|
||||
/* Program Receive Enable Timings */
|
||||
sdram_program_receive_enable(&sysinfo);
|
||||
|
|
|
|||
|
|
@ -47,6 +47,9 @@ struct sys_info {
|
|||
u8 mvco4x; /* 0 (8x) or 1 (4x) */
|
||||
u8 clkcfg_bit7;
|
||||
u8 boot_path;
|
||||
#define BOOT_PATH_NORMAL 0
|
||||
#define BOOT_PATH_RESET 1
|
||||
#define BOOT_PATH_RESUME 2
|
||||
|
||||
u8 package; /* 0 = planar, 1 = stacked */
|
||||
#define SYSINFO_PACKAGE_PLANAR 0x00
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse)
|
|||
reg32 |= ((u32)coarse & 0x0f) << 24;
|
||||
MCHBAR32(C0DRT1 + channel_offset) = reg32;
|
||||
|
||||
/* This should never happen: */
|
||||
if (coarse > 0x0f)
|
||||
printk_debug("set_receive_enable: coarse overflow: 0x%02x.\n", coarse);
|
||||
|
||||
|
|
@ -87,11 +88,11 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse)
|
|||
|
||||
reg32 = MCHBAR32(RCVENMT);
|
||||
if (!channel_offset) {
|
||||
|
||||
/* Channel 0 */
|
||||
reg32 &= ~(3 << 2);
|
||||
reg32 |= medium << 2;
|
||||
} else {
|
||||
|
||||
/* Channel 1 */
|
||||
reg32 &= ~(3 << 0);
|
||||
reg32 |= medium;
|
||||
}
|
||||
|
|
@ -132,7 +133,6 @@ static int find_preamble(int channel_offset, u8 * mediumcoarse,
|
|||
|
||||
do {
|
||||
if (*mediumcoarse < 4) {
|
||||
|
||||
printk_debug("No Preamble found.\n");
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -146,7 +146,6 @@ static int find_preamble(int channel_offset, u8 * mediumcoarse,
|
|||
} while (reg32 & (1 << 19));
|
||||
|
||||
if (!(reg32 & (1 << 18))) {
|
||||
|
||||
printk_debug("No Preamble found (neither high nor low).\n");
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -200,7 +199,6 @@ static int find_strobes_low(int channel_offset, u8 * mediumcoarse, u8 * fine,
|
|||
if (((rcvenmt & (1 << 18)) != 0))
|
||||
return 0;
|
||||
|
||||
|
||||
*fine -= 0x80;
|
||||
if (*fine == 0)
|
||||
continue;
|
||||
|
|
@ -220,6 +218,7 @@ static int find_strobes_low(int channel_offset, u8 * mediumcoarse, u8 * fine,
|
|||
static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine,
|
||||
struct sys_info *sysinfo)
|
||||
{
|
||||
|
||||
int counter;
|
||||
u32 rcvenmt;
|
||||
|
||||
|
|
@ -258,7 +257,7 @@ static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine,
|
|||
continue;
|
||||
}
|
||||
|
||||
printk_debug("could not find rising edge.\n");
|
||||
printk_debug("Could not find rising edge.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
@ -336,3 +335,4 @@ void receive_enable_adjust(struct sys_info *sysinfo)
|
|||
if (receive_enable_autoconfig(0x80, sysinfo))
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue