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mb/siemens/mc_ehl2: Adjust PCH serial IO settings 

Correct the PCH serial IO settings, suitable for this mainboard.

Change-Id: I3c9915b2d52fbc6a15ac1e68c77bfb3983f7b1cd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer 2021-08-25 15:36:31 +02:00 committed by Felix Held
parent 76b4e414f3
commit 71b227d6eb
1 changed files with 6 additions and 17 deletions
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23
src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
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@ -98,30 +98,19 @@ chip soc/intel/elkhartlake
# LPSS Serial IO (I2C/UART/GSPI) related UPDs
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexI2C6] = PchSerialIoDisabled,
[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
}"
register "SerialIoI2cPadsTermination" = "{
[PchSerialIoIndexI2C0] = 1,
[PchSerialIoIndexI2C1] = 1,
[PchSerialIoIndexI2C2] = 1,
[PchSerialIoIndexI2C3] = 1,
[PchSerialIoIndexI2C4] = 1,
[PchSerialIoIndexI2C5] = 1,
[PchSerialIoIndexI2C6] = 1,
[PchSerialIoIndexI2C7] = 1,
}"
register "SerialIoUartMode" = "{
[PchSerialIoIndexUART0] = PchSerialIoDisabled,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoPci,
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"