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soc/intel: Update all references to ESE as ISSE 

Intel has rebranded ESE as ISSE (Intel Silicon Security Engine),so all
references to ESE is updated to ISSE in the current coreboot code.

BUG=None
TEST=Build all the variants based on Intel Meteor Lake SoC

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I1f8785704706d56a35e94a0f3386bc551cd1f263
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77241
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Usha P 2023-08-16 08:25:19 +05:30 committed by Subrata Banik
parent 829adab311
commit 71b9fbabb7
5 changed files with 23 additions and 23 deletions
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4
src/commonlib/include/commonlib/timestamp_serialized.h
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@ -143,7 +143,7 @@ enum timestamp_id {
/* 990+ reserved for vendorcode extensions (990-999: Intel ME continued) */ /* 990+ reserved for vendorcode extensions (990-999: Intel ME continued) */
TS_ME_ROM_START = 990, TS_ME_ROM_START = 990,
TS_ESE_DMU_LOAD_END = 991, TS_ISSE_DMU_LOAD_END = 991,
/* 1000+ reserved for payloads */ /* 1000+ reserved for payloads */
@ -333,7 +333,7 @@ static const struct timestamp_id_to_name {
/* Intel ME continued */ /* Intel ME continued */
TS_NAME_DEF(TS_ME_ROM_START, 0, "CSME ROM started execution"), TS_NAME_DEF(TS_ME_ROM_START, 0, "CSME ROM started execution"),
TS_NAME_DEF(TS_ESE_DMU_LOAD_END, 0, "Die Management Unit (DMU) load completed"), TS_NAME_DEF(TS_ISSE_DMU_LOAD_END, 0, "Die Management Unit (DMU) load completed"),
/* Depthcharge entry timestamp */ /* Depthcharge entry timestamp */
TS_NAME_DEF(TS_DC_START, 0, "depthcharge start"), TS_NAME_DEF(TS_DC_START, 0, "depthcharge start"),

4
src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h
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@ -13,8 +13,8 @@ enum cse_boot_perf_data_v1 {
/* CSME ROM completed execution / CSME RBE started */ /* CSME ROM completed execution / CSME RBE started */
PERF_DATA_CSME_ROM_COMPLETED = 2, PERF_DATA_CSME_ROM_COMPLETED = 2,
/* CSME got ESE Init Done indication from ESE */ /* CSME got ISSE Init Done indication from ISSE */
PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3, PERF_DATA_CSME_GOT_ISSE_INIT_DONE = 3,
/* CSME RBE start PMC patch/es loading */ /* CSME RBE start PMC patch/es loading */
PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_START = 4, PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_START = 4,

20
src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h
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@ -13,8 +13,8 @@ enum cse_boot_perf_data_v2 {
/* CSME ROM completed execution / CSME RBE started */ /* CSME ROM completed execution / CSME RBE started */
PERF_DATA_CSME_ROM_COMPLETED = 2, PERF_DATA_CSME_ROM_COMPLETED = 2,
/* CSME got ESE Init Done indication from ESE */ /* CSME got ISSE Init Done indication from ISSE */
PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3, PERF_DATA_CSME_GOT_ISSE_INIT_DONE = 3,
/* CSME RBE started SOC.PMC patch and payloads read from SPI flash */ /* CSME RBE started SOC.PMC patch and payloads read from SPI flash */
PERF_DATA_CSME_RBE_SOC_PMC_PATCH_LOADING_START = 4, PERF_DATA_CSME_RBE_SOC_PMC_PATCH_LOADING_START = 4,
@ -43,11 +43,11 @@ enum cse_boot_perf_data_v2 {
/* CSME BUP start running */ /* CSME BUP start running */
PERF_DATA_CSME_BUP_START = 12, PERF_DATA_CSME_BUP_START = 12,
/* CSME established IPC channel communication with ESE */ /* CSME established IPC channel communication with ISSE */
PERF_DATA_CSME_IPC_CHANNEL_FOR_ESE_UP = 13, PERF_DATA_CSME_IPC_CHANNEL_FOR_ISSE_UP = 13,
/* ESE FW initialization completed */ /* ISSE FW initialization completed */
PERF_DATA_ESE_FW_INIT_DONE = 14, PERF_DATA_ISSE_FW_INIT_DONE = 14,
/* PMC set PPS */ /* PMC set PPS */
PERF_DATA_PMC_SET_PPS = 15, PERF_DATA_PMC_SET_PPS = 15,
@ -73,8 +73,8 @@ enum cse_boot_perf_data_v2 {
/* PMC indicated CSME that SYS_PWROK was asserted */ /* PMC indicated CSME that SYS_PWROK was asserted */
PERF_DATA_PMC_SYS_PWROK_ASSERTED = 22, PERF_DATA_PMC_SYS_PWROK_ASSERTED = 22,
/* ESE sent IPC message to CSME indicating PUnit load completed */ /* ISSE sent IPC message to CSME indicating PUnit load completed */
PERF_DATA_ESE_PUNIT_LOAD_COMPLETED = 23, PERF_DATA_ISSE_PUNIT_LOAD_COMPLETED = 23,
/* PMC indicates CSME that xxPLTRST was de-asserted */ /* PMC indicates CSME that xxPLTRST was de-asserted */
PERF_DATA_PMC_PLTRST_DEASSERTED = 24, PERF_DATA_PMC_PLTRST_DEASSERTED = 24,
@ -94,8 +94,8 @@ enum cse_boot_perf_data_v2 {
/* PMC sent "Core Reset Done Ack - Sent" message to CSME */ /* PMC sent "Core Reset Done Ack - Sent" message to CSME */
PERF_DATA_PMC_SENT_CRDA = 29, PERF_DATA_PMC_SENT_CRDA = 29,
/* ESE sent IPC message to CSME indicating DMU load completed */ /* ISSE sent IPC message to CSME indicating DMU load completed */
PERF_DATA_ESE_DMU_LOAD_COMPLETED = 30, PERF_DATA_ISSE_DMU_LOAD_COMPLETED = 30,
/* ACM Active indication - ACM started its execution */ /* ACM Active indication - ACM started its execution */
PERF_DATA_ACM_START = 31, PERF_DATA_ACM_START = 31,

4
src/soc/intel/meteorlake/cse_telemetry.c
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@ -24,6 +24,6 @@ void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time)
start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]);
timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC,
start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]);
timestamp_add(TS_ESE_DMU_LOAD_END, timestamp_add(TS_ISSE_DMU_LOAD_END,
start_stamp + ts[PERF_DATA_ESE_DMU_LOAD_COMPLETED]); start_stamp + ts[PERF_DATA_ISSE_DMU_LOAD_COMPLETED]);
} }

14
src/soc/intel/meteorlake/include/soc/pci_devs.h
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@ -144,13 +144,13 @@
#define PCI_DEVFN_SATA _PCI_DEVFN(SATA, 0) #define PCI_DEVFN_SATA _PCI_DEVFN(SATA, 0)
#define PCI_DEV_SATA _PCI_DEV(SATA, 0) #define PCI_DEV_SATA _PCI_DEV(SATA, 0)
#define PCI_DEV_SLOT_ESE 0x18 #define PCI_DEV_SLOT_ISSE 0x18
#define PCI_DEVFN_ESE1 _PCI_DEVFN(ESE, 0) #define PCI_DEVFN_ISSE1 _PCI_DEVFN(ESE, 0)
#define PCI_DEVFN_ESE2 _PCI_DEVFN(ESE, 1) #define PCI_DEVFN_ISSE2 _PCI_DEVFN(ESE, 1)
#define PCI_DEVFN_ESE3 _PCI_DEVFN(ESE, 2) #define PCI_DEVFN_ISSE3 _PCI_DEVFN(ESE, 2)
#define PCI_DEV_ESE1 _PCI_DEV(ESE, 0) #define PCI_DEV_ISSE1 _PCI_DEV(ESE, 0)
#define PCI_DEV_ESE2 _PCI_DEV(ESE, 1) #define PCI_DEV_ISSE2 _PCI_DEV(ESE, 1)
#define PCI_DEV_ESE3 _PCI_DEV(ESE, 2) #define PCI_DEV_ISSE3 _PCI_DEV(ESE, 2)
#define PCI_DEV_SLOT_SIO1 0x19 #define PCI_DEV_SLOT_SIO1 0x19
#define PCI_DEVFN_I2C4 _PCI_DEVFN(SIO1, 0) #define PCI_DEVFN_I2C4 _PCI_DEVFN(SIO1, 0)