soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg
In order for the SOC to be able to control the Aux line orientation for Type-C ports that do not have a retimer, the IomTypeCPortPadCfg UPD needs to be configurable through devicetree to correctly set the GPIO pins that the SOC should use to flip orientation. BUG=b:145220205 BRANCH=NONE TEST=booted Volteer proto 2 and verified that the AUX channels flip when the cable is flipped Change-Id: I2e48adb624c7922170eafb8dfcaed680f008936e Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40244 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -221,6 +221,19 @@ struct soc_intel_tigerlake_config {
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uint8_t TcssDma0En;
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uint8_t TcssDma1En;
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/*
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* IOM Port Config
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* If a port orientation needs to be controlled by the SOC this setting must be
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* updated to reflect the correct GPIOs being used for the SOC port flipping.
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* There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down
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* 0,1 are pull up and pull down for port 0
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* 2,3 are pull up and pull down for port 1
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* 4,5 are pull up and pull down for port 2
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* 6,7 are pull up and pull down for port 3
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* values to be programmed correspond to the GPIO family and offsets
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*/
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uint32_t IomTypeCPortPadCfg[8];
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/*
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* SOC Aux orientation override:
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* This is a bitfield that corresponds to up to 4 TCSS ports on TGL.
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@ -103,7 +103,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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params->TcssAuxOri = config->TcssAuxOri;
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for (i = 0; i < 8; i++)
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params->IomTypeCPortPadCfg[i] = 0x09000000;
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params->IomTypeCPortPadCfg[i] = config->IomTypeCPortPadCfg[i];
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/* Chipset Lockdown */
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if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
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