failed attempt to do early init for cs5535. Almost there but
still get garbage reading smbus. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
parent
ec9cdc980f
commit
71eae20b30
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@ -0,0 +1,31 @@
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#ifndef CPU_AMD_GX2DEF_H
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#define CPU_AMD_GX2DEF_H
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/* GeodeLink Control Processor Registers, GLIU1, Port 3 */
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#define GLCP_CLK_DIS_DELAY 0x4c000008
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#define GLCP_PMCLKDISABLE 0x4c000009
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#define GLCP_DELAY_CONTROLS 0x4c00000f
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#define GLCP_SYS_RSTPLL 0x4c000014
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#define GLCP_DOTPLL 0x4c000015
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/* Upper 32 bits */
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#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9
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#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6
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#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0
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/* Lower 32 bits */
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#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
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#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
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#define GLCP_SYS_RSTPLL_LOCKWAIT 24
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#define GLCP_SYS_RSTPLL_HOLDCOUNT 16
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#define GLCP_SYS_RSTPLL_BYPASS 15
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#define GLCP_SYS_RSTPLL_PD 14
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#define GLCP_SYS_RSTPLL_RESETPLL 13
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#define GLCP_SYS_RSTPLL_DDRMODE 10
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#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9
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#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8
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#define GLCP_SYS_RSTPLL_CHIP_RESET 0
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#endif /* CPU_AMD_GX2DEF_H */
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@ -9,48 +9,32 @@
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "cpu/x86/bist.h"
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#include "cpu/x86/msr.h"
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#include <cpu/amd/gx2def.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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static void dump_msr(void)
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{
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int i = 0;
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msr_t msr;
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static const unsigned int msrs[] = { 0x20000018, 0x20000019, 0x0};
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while (msrs[i] != 0) {
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msr = rdmsr(msrs[i]);
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print_debug("MSR ");
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print_debug_hex32(msrs[i]);
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print_debug("=> ");
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print_debug_hex32(msr.hi);
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print_debug(":");
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print_debug_hex32(msr.lo);
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print_debug("\n\r");
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i++;
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}
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}
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//#include "lib/delay.c"
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#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
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#include "southbridge/amd/cs5535/cs5535_early_setup.c"
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#include "northbridge/amd/gx2/raminit.h"
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#include "northbridge/amd/gx2/raminit.c"
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#include "sdram/generic_sdram.c"
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#include "northbridge/amd/gx2/pll_reset.c"
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static void msr_init(void)
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{
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__builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
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__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
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__builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
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__builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
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__builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
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__builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
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__builtin_wrmsr(0x10000080, 0x3, 0x0);
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__builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
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@ -60,47 +44,12 @@ static void msr_init(void)
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__builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
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__builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
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__builtin_wrmsr(0x400000e3, 0xf0309c10, 0x0);
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__builtin_wrmsr(0xc0002001, 0x86002, 0x0);
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__builtin_wrmsr(0x80002001, 0x86002, 0x0);
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__builtin_wrmsr(0xa0002001, 0x86002, 0x0);
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__builtin_wrmsr(0x50002001, 0x27, 0x0);
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__builtin_wrmsr(0x4c002001, 0x1, 0x0);
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}
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static void pll_reset(void)
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{
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msr_t msr;
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msr = rdmsr(0x4c000014);
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print_debug("CGLP_SYS_RSTPLL ");
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print_debug_hex32(msr.hi);
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print_debug(":");
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print_debug_hex32(msr.lo);
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print_debug("\n\r");
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if ((msr.lo >> 26) & 0x3F) {
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print_debug("reboot from BIOS reset\n\r");
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return;
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}
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print_debug("prgramming PLL\n\r");
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msr.hi = 0x00000019;
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msr.lo = 0x06de0378;
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wrmsr(0x4c000014, msr);
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msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
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wrmsr(0x4c000014, msr);
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print_debug("Reset PLL\n\r");
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msr.lo |= ((1<<14) |(1<<13) | (1<<0));
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wrmsr(0x4c000014,msr);
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print_debug("should not be here\n\r");
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}
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static void main(unsigned long bist)
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{
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static const struct mem_controller memctrl [] = {
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@ -113,10 +62,10 @@ static void main(unsigned long bist)
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uart_init();
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console_init();
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cs5535_early_setup();
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pll_reset();
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msr_init();
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//msr_init();
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/* Halt if there was a built in self test failure */
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//report_bist_failure(bist);
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@ -102,7 +102,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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/* load RDSYNC */
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msr = rdmsr(0x2000001f);
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msr.hi = 0x000ff300;
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msr.hi = 0x000ff310;
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msr.lo = 0x00000000;
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wrmsr(0x2000001f, msr);
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@ -3,35 +3,39 @@
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#define SMBUS_IO_BASE 0x6000
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/* initialization for SMBus Controller */
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static int enable_smbus(void)
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static int cs5535_enable_smbus(void)
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{
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unsigned char val;
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/* FixME: move to early_iobase.c */
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/* setup LBAR for SMBus controller */
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__builtin_wrmsr(0x5140000B, 0x00006000, 0x0000f001);
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/* setup LBAR for GPIO at 0x6100 */
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__builtin_wrmsr(0x5140000C, 0x00006100, 0x0000f001);
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outb(0, SMBUS_IO_BASE + SMB_CTRL2);
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/* Set SCL freq and enable SMB controller */
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val = inb(SMBUS_IO_BASE + SMB_CTRL2);
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val |= ((0x7F << 1) | SMB_CTRL2_ENABLE);
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outb(val, SMBUS_IO_BASE + SMB_CTRL2);
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/* setup GPIO pins for SDA/SCL */
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/* Setup SMBus host controller address to 0xEF */
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/* Setup SMBus host controller address to 0xEF */
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val = inb(SMBUS_IO_BASE + SMB_ADD);
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val |= (0xEF | SMB_ADD_SAEN);
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outb(val, SMBUS_IO_BASE + SMB_ADD);
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/* Set SCL freq and enable SMB controller */
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outb(0x00, SMBUS_IO_BASE + SMB_CTRL2);
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val = inb(SMBUS_IO_BASE + SMB_CTRL2);
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val |= (0x7F < 1) | SMB_CTRL2_ENABLE;
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outb(val, SMBUS_IO_BASE + SMB_CTRL2);
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/* Is SDA pulled high ? */
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val = inb(SMBUS_IO_BASE + SMB_CTRL_STS);
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if (val & SMB_CSTS_TSDA)
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return SMBUS_ERROR;
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#if 0
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print_debug("SMBUS registers ");
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print_debug_hex8(inb(SMBUS_IO_BASE));
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print_debug(" ");
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print_debug_hex8(inb(SMBUS_IO_BASE + 1));
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print_debug(" ");
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print_debug_hex8(inb(SMBUS_IO_BASE + 2));
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print_debug(" ");
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print_debug_hex8(inb(SMBUS_IO_BASE + 3));
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print_debug(" ");
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print_debug_hex8(inb(SMBUS_IO_BASE + 4));
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print_debug(" ");
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print_debug_hex8(inb(SMBUS_IO_BASE + 5));
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print_debug(" ");
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print_debug_hex8(inb(SMBUS_IO_BASE + 6));
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print_debug("\n\r");
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#endif
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}
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#if 0
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@ -3,46 +3,49 @@
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#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
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#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
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enum smb_native_registers {
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SMB_SDA = 0x00, SMB_STS = 0x01, SMB_CTRL_STS = 0x02,
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SMB_CTRL1 = 0x03, SMB_ADD = 0x04, SMB_CTRL2 = 0x05,
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SMB_CTRL3 = 0x06
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};
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#define SMB_SDA 0x00
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#define SMB_STS 0x01
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#define SMB_CTRL_STS 0x02
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#define SMB_CTRL1 0x03
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#define SMB_ADD 0x04
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#define SMB_CTRL2 0x05
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#define SMB_CTRL3 0x06
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enum smb_sts_bits {
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SMB_STS_SLVSTP = (0x01 << 7), SMB_STS_SDAST = (0x01 << 6),
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SMB_STS_BER = (0x01 << 5), SMB_STS_NEGACK = (0x01 << 4),
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SMB_STS_STASTR = (0x01 << 3), SMB_STS_NMATCH = (0x01 << 2),
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SMB_STS_MASTER = (0x01 << 1), SMB_STS_XMIT = (0x01 << 0)
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};
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#define SMB_STS_SLVSTP (0x01 << 7)
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#define SMB_STS_SDAST (0x01 << 6)
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#define SMB_STS_BER (0x01 << 5)
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#define SMB_STS_NEGACK (0x01 << 4)
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#define SMB_STS_STASTR (0x01 << 3)
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#define SMB_STS_NMATCH (0x01 << 2)
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#define SMB_STS_MASTER (0x01 << 1)
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#define SMB_STS_XMIT (0x01 << 0)
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enum smb_ctrl_sts_bits {
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SMB_CSTS_TGSCL = (0x01 << 5), SMB_CSTS_TSDA = (0x01 << 4),
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SMB_CSTS_GCMTCH = (0x01 << 3), SMB_CSTS_MATCH = (0x01 << 2),
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SMB_CSTS_BB = (0x01 << 1), SMB_CSTS_BUSY = (0x01 << 0)
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};
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#define SMB_CSTS_TGSCL (0x01 << 5)
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#define SMB_CSTS_TSDA (0x01 << 4)
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#define SMB_CSTS_GCMTCH (0x01 << 3)
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#define SMB_CSTS_MATCH (0x01 << 2)
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#define SMB_CSTS_BB (0x01 << 1)
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#define SMB_CSTS_BUSY (0x01 << 0)
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enum smb_ctrl1_bits {
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SMB_CTRL1_STASTRE = (0x01 << 7), SMB_CTRL1_NMINTE = (0x01 << 6),
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SMB_CTRL1_GCMEN = (0x01 << 5), SMB_CTRL1_ACK = (0x01 << 4),
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SMB_CTRL1_RSVD = (0x01 << 3), SMB_CTRL1_INTEN = (0x01 << 2),
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SMB_CTRL1_STOP = (0x01 << 1), SMB_CTRL1_START = (0x01 << 0)
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};
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#define SMB_CTRL1_STASTRE (0x01 << 7)
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#define SMB_CTRL1_NMINTE (0x01 << 6)
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#define SMB_CTRL1_GCMEN (0x01 << 5)
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#define SMB_CTRL1_ACK (0x01 << 4)
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#define SMB_CTRL1_RSVD (0x01 << 3)
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#define SMB_CTRL1_INTEN (0x01 << 2)
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#define SMB_CTRL1_STOP (0x01 << 1)
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#define SMB_CTRL1_START (0x01 << 0)
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enum smb_add_bits {
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SMB_ADD_SAEN = (0x01 << 7)
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};
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#define SMB_ADD_SAEN (0x01 << 7)
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enum smb_ctrl2_bits {
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SMB_CTRL2_ENABLE = 0x01,
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};
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#define SMB_CTRL2_ENABLE 0x01
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#define SMBUS_TIMEOUT (100*1000*10)
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#define SMBUS_STATUS_MASK 0xfbff
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static inline void smbus_delay(void)
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static void smbus_delay(void)
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{
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outb(0x80, 0x80);
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outb(0x80, 0x80);
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}
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/* generate a smbus start condition */
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@ -124,19 +127,24 @@ static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
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return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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}
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static int do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
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static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
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{
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unsigned char val;
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smbus_start_condition(smbus_io_base);
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if (smbus_start_condition(smbus_io_base) < 0)
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print_debug("smbus error 1");
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smbus_send_slave_address(smbus_io_base, device);
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if (smbus_send_slave_address(smbus_io_base, device) < 0)
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print_debug("smbus error 2");
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smbus_send_command(smbus_io_base, address);
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if (smbus_send_command(smbus_io_base, address) < 0)
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print_debug("smbus error 3");
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smbus_start_condition(smbus_io_base);
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if (smbus_start_condition(smbus_io_base) < 0)
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print_debug("smbus error 4");
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smbus_send_slave_address(smbus_io_base, device | 0x01);
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if (smbus_send_slave_address(smbus_io_base, device | 0x01))
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print_debug("smbus error 5");
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val = inb(smbus_io_base + SMB_CTRL1);
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outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
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