Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.
2065x is with nehalem and not sandybridge. I don't care much eitherway but it clears some confusion. Change-Id: Ib2b8e570b830a12ed8d0d313ee4eb56755796d4b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4046 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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@ -237,7 +237,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
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/* Max Non-Turbo Ratio */
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ratio_max = (msr.lo >> 8) & 0xff;
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}
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clock_max = ratio_max * SANDYBRIDGE_BCLK + ratio_max / 3;
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clock_max = ratio_max * NEHALEM_BCLK + ratio_max / 3;
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/* Calculate CPU TDP in mW */
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power_max = 25000;
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@ -298,7 +298,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
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/* Calculate power at this ratio */
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power = calculate_power(power_max, ratio_max, ratio);
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clock = ratio * SANDYBRIDGE_BCLK + ratio / 3;
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clock = ratio * NEHALEM_BCLK + ratio / 3;
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len_pss += acpigen_write_PSS_package(
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clock, /*MHz*/
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@ -22,8 +22,8 @@
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#ifndef _CPU_INTEL_MODEL_2065X_H
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#define _CPU_INTEL_MODEL_2065X_H
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/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
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#define SANDYBRIDGE_BCLK 133
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/* Nehalem bus clock is fixed at 133MHz */
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#define NEHALEM_BCLK 133
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#define IA32_FEATURE_CONTROL 0x3a
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#define CPUID_VMX (1 << 5)
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@ -311,7 +311,7 @@ static void set_max_ratio(void)
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wrmsr(IA32_PERF_CTL, perf_ctl);
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printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n",
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((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
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((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK);
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}
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static void set_energy_perf_bias(u8 policy)
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@ -27,5 +27,5 @@ unsigned long tsc_freq_mhz(void)
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msr_t platform_info;
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platform_info = rdmsr(MSR_PLATFORM_INFO);
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return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff);
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return NEHALEM_BCLK * ((platform_info.lo >> 8) & 0xff);
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}
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