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mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only pads 

There is a whole bunch of pads being configured by the vendor firmware
that are either unconnected due to unpopulated resistor pads, only
connected to test points for vendor debugging purposes or just used as
strap. Configure them as NC with an appropriate pull to disable the
RX/TX functions.

The pads have been determined by dissecting a dead board.

This patch has been tested thoughroughly on a machine, normally used
productive, to see if any issues arise. No problems occurred at all.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I06b942e3182469f87e41914c893e5b485ccca420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Michael Niewöhner 2020-11-08 19:32:13 +01:00
parent 0b04d1bf88
commit 71f639f123
1 changed files with 35 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

70
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c
View File

@ -22,9 +22,9 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_A13, UP_20K),
PAD_NC(GPP_A14, UP_20K),
PAD_NC(GPP_A15, UP_20K),
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
PAD_NC(GPP_A16, UP_20K),
PAD_NC(GPP_A17, UP_20K),
PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF),
PAD_NC(GPP_A18, NONE),
/* GPP_A19 - RESERVED */
PAD_NC(GPP_A20, UP_20K),
PAD_NC(GPP_A21, UP_20K),
@ -32,8 +32,8 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_A23, UP_20K),
/* GPIO Group GPP_B */
PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE),
PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE),
PAD_NC(GPP_B0, UP_20K),
PAD_NC(GPP_B1, UP_20K),
PAD_NC(GPP_B2, NONE),
PAD_NC(GPP_B3, UP_20K),
PAD_NC(GPP_B4, UP_20K),
@ -43,7 +43,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_B8, UP_20K),
PAD_NC(GPP_B9, UP_20K),
PAD_NC(GPP_B10, UP_20K),
PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE),
PAD_NC(GPP_B11, DN_20K),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), /* SPKR + JBR1 ("Top-Block Swap") */
@ -63,12 +63,12 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C2, NONE),
/* GPP_C3 - RESERVED */
/* GPP_C4 - RESERVED */
PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE),
PAD_NC(GPP_C5, NONE),
/* GPP_C6 - RESERVED */
/* GPP_C7 - RESERVED */
PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF),
PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF),
PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF),
PAD_NC(GPP_C8, NONE),
PAD_NC(GPP_C9, NONE),
PAD_NC(GPP_C10, NONE),
PAD_NC(GPP_C11, NONE),
PAD_NC(GPP_C12, UP_20K),
PAD_NC(GPP_C13, UP_20K),
@ -130,7 +130,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_F2, UP_20K),
PAD_NC(GPP_F3, UP_20K),
PAD_NC(GPP_F4, UP_20K),
PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST),
PAD_NC(GPP_F5, NONE),
PAD_NC(GPP_F6, UP_20K),
PAD_NC(GPP_F7, UP_20K),
PAD_NC(GPP_F8, UP_20K),
@ -148,7 +148,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_F20, UP_20K),
PAD_NC(GPP_F21, UP_20K),
PAD_NC(GPP_F22, UP_20K),
PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE),
PAD_NC(GPP_F23, NONE),
/* GPIO Group GPP_G */
PAD_NC(GPP_G0, NONE), /* JPCIE6-A19 (DGPU_PWR_EN#) */
@ -168,7 +168,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_G14, NONE, PLTRST), /* SKU_ID[2] */
PAD_CFG_GPI(GPP_G15, NONE, PLTRST), /* SKU_ID[3] */
PAD_CFG_GPI(GPP_G16, NONE, PLTRST), /* SKU_ID[4] */
PAD_NC(GPP_G17, NONE),
PAD_NC(GPP_G17, UP_20K),
PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* BMC NMI# */
PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), /* BMC SMI# */
PAD_CFG_GPI(GPP_G20, NONE, PLTRST), /* JPI2C1 PWRFAIL# */
@ -177,21 +177,21 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_G23, NONE),
/* GPIO Group GPP_H */
PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE),
PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF),
PAD_NC(GPP_H0, UP_20K),
PAD_NC(GPP_H1, NONE),
PAD_NC(GPP_H2, UP_20K),
PAD_NC(GPP_H3, UP_20K),
PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF),
PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE),
PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE),
PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE),
PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE),
PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE),
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
PAD_NC(GPP_H4, UP_20K),
PAD_NC(GPP_H5, UP_20K),
PAD_NC(GPP_H6, UP_20K),
PAD_NC(GPP_H7, UP_20K),
PAD_NC(GPP_H8, UP_20K),
PAD_NC(GPP_H9, UP_20K),
PAD_NC(GPP_H10, NONE),
PAD_NC(GPP_H11, UP_20K),
PAD_NC(GPP_H12, UP_20K),
PAD_NC(GPP_H13, NONE),
PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1),
PAD_NC(GPP_H14, NONE),
PAD_NC(GPP_H15, NONE),
PAD_NC(GPP_H16, NONE),
PAD_NC(GPP_H17, NONE),
@ -200,20 +200,20 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_H20, UP_20K),
PAD_NC(GPP_H21, UP_20K),
PAD_NC(GPP_H22, UP_20K),
PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE),
PAD_NC(GPP_H23, NONE),
/* GPIO Group GPP_I */
PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1),
PAD_NC(GPP_I0, NONE),
PAD_NC(GPP_I1, NONE),
PAD_NC(GPP_I2, NONE),
PAD_NC(GPP_I3, NONE),
PAD_NC(GPP_I4, NONE),
PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
PAD_NC(GPP_I5, NONE),
PAD_NC(GPP_I6, UP_20K),
PAD_NC(GPP_I7, NONE),
PAD_NC(GPP_I8, UP_20K),
PAD_NC(GPP_I9, NONE),
PAD_NC(GPP_I10, UP_20K),
/* GPIO Group GPD */
PAD_NC(GPD0, NONE),
@ -224,7 +224,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
PAD_NC(GPD7, UP_20K),
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
PAD_NC(GPD8, UP_20K),
PAD_NC(GPD9, UP_20K),
PAD_NC(GPD10, UP_20K),
PAD_NC(GPD11, NONE),