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Revert "mb/google/brya/brya0: Manually probe fw_config for DB_LTE" 

This reverts commit 2f8a7046bb.

Reason for revert: CB:54752 makes this unnecessary

Change-Id: I3ad0bcafe50e3eafb9a106720c6c9ea5cb0efc4f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54789
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2021-05-21 19:34:38 +00:00
parent 7f6ae79280
commit 71f69ddc79
5 changed files with 3 additions and 21 deletions
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2
src/mainboard/google/brya/romstage.c
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@ -17,6 +17,4 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
}; };
memcfg_init(&memupd->FspmConfig, mem_config, &spd_info, half_populated); memcfg_init(&memupd->FspmConfig, mem_config, &spd_info, half_populated);
variant_update_fspm_upds(memupd);
} }

3
src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
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@ -3,7 +3,6 @@
#ifndef __BASEBOARD_VARIANTS_H__ #ifndef __BASEBOARD_VARIANTS_H__
#define __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__
#include <fsp/api.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <soc/meminit.h> #include <soc/meminit.h>
#include <stdint.h> #include <stdint.h>
@ -20,6 +19,4 @@ const struct mb_cfg *variant_memory_params(void);
int variant_memory_sku(void); int variant_memory_sku(void);
bool variant_is_half_populated(void); bool variant_is_half_populated(void);
void variant_update_fspm_upds(FSPM_UPD *memupd);
#endif /*__BASEBOARD_VARIANTS_H__ */ #endif /*__BASEBOARD_VARIANTS_H__ */

2
src/mainboard/google/brya/variants/brya0/Makefile.inc
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@ -1,2 +0,0 @@
romstage-y += variant.c
ramstage-y += variant.c

3
src/mainboard/google/brya/variants/brya0/overridetree.cb
View File

@ -122,6 +122,9 @@ chip soc/intel/alderlake
device generic 0 on end device generic 0 on end
end end
end end
device ref pcie_rp6 on
probe DB_LTE LTE_PCIE
end
device ref pcie_rp8 on device ref pcie_rp8 on
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"

14
src/mainboard/google/brya/variants/brya0/variant.c
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@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
#include <console/console.h>
#include <fw_config.h>
void variant_update_fspm_upds(FSPM_UPD *memupd)
{
if (fw_config_probe(FW_CONFIG(DB_LTE, LTE_USB))) {
FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
printk(BIOS_INFO, "Disabling PCIe RP 6 UPD for USB WWAN\n");
m_cfg->PcieRpEnableMask &= ~BIT(5);
}
}