Revert "mb/google/brya/brya0: Manually probe fw_config for DB_LTE"
This reverts commit 2f8a7046bb
.
Reason for revert: CB:54752 makes this unnecessary
Change-Id: I3ad0bcafe50e3eafb9a106720c6c9ea5cb0efc4f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54789
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
7f6ae79280
commit
71f69ddc79
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@ -17,6 +17,4 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
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};
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memcfg_init(&memupd->FspmConfig, mem_config, &spd_info, half_populated);
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variant_update_fspm_upds(memupd);
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}
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@ -3,7 +3,6 @@
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#ifndef __BASEBOARD_VARIANTS_H__
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#define __BASEBOARD_VARIANTS_H__
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#include <fsp/api.h>
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#include <soc/gpio.h>
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#include <soc/meminit.h>
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#include <stdint.h>
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@ -20,6 +19,4 @@ const struct mb_cfg *variant_memory_params(void);
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int variant_memory_sku(void);
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bool variant_is_half_populated(void);
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void variant_update_fspm_upds(FSPM_UPD *memupd);
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#endif /*__BASEBOARD_VARIANTS_H__ */
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@ -1,2 +0,0 @@
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romstage-y += variant.c
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ramstage-y += variant.c
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@ -122,6 +122,9 @@ chip soc/intel/alderlake
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device generic 0 on end
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end
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end
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device ref pcie_rp6 on
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probe DB_LTE LTE_PCIE
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end
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device ref pcie_rp8 on
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
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@ -1,14 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/variants.h>
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#include <console/console.h>
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#include <fw_config.h>
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void variant_update_fspm_upds(FSPM_UPD *memupd)
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{
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if (fw_config_probe(FW_CONFIG(DB_LTE, LTE_USB))) {
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FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
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printk(BIOS_INFO, "Disabling PCIe RP 6 UPD for USB WWAN\n");
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m_cfg->PcieRpEnableMask &= ~BIT(5);
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}
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}
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