diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c
index 4b260da1af..d926dbbe2d 100644
--- a/src/soc/intel/alderlake/lockdown.c
+++ b/src/soc/intel/alderlake/lockdown.c
@@ -8,10 +8,16 @@
 
 #include <device/mmio.h>
 #include <intelblocks/cfg.h>
+#include <intelblocks/pcr.h>
 #include <intelpch/lockdown.h>
+#include <soc/pcr_ids.h>
 #include <soc/pm.h>
 #include <stdint.h>
 
+/* PCR PSTH Control Register */
+#define PCR_PSTH_CTRLREG		0x1d00
+#define   PSTH_CTRLREG_IOSFPTCGE	(1 << 2)
+
 static void pmc_lockdown_cfg(int chipset_lockdown)
 {
 	uint8_t *pmcbase = pmc_mmio_regs();
@@ -32,8 +38,19 @@ static void pmc_lockdown_cfg(int chipset_lockdown)
 	}
 }
 
+static void pch_lockdown_cfg(void)
+{
+	if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
+		return;
+
+	/* Enable IOSF Primary Trunk Clock Gating */
+	pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
+}
+
 void soc_lockdown_config(int chipset_lockdown)
 {
 	/* PMC lock down configuration */
 	pmc_lockdown_cfg(chipset_lockdown);
+	/* PCH lock down configuration */
+	pch_lockdown_cfg();
 }