From 71fd0fa78008151286ce7b341f31b5cec0ff6553 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 18 Apr 2022 13:31:57 +0530
Subject: [PATCH] soc/intel/alderlake: Implement PCH lock down configuration

This patch implements a function to enable IOSF Primary Trunk Clock
Gating.

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
---
 src/soc/intel/alderlake/lockdown.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c
index 4b260da1af..d926dbbe2d 100644
--- a/src/soc/intel/alderlake/lockdown.c
+++ b/src/soc/intel/alderlake/lockdown.c
@@ -8,10 +8,16 @@
 
 #include <device/mmio.h>
 #include <intelblocks/cfg.h>
+#include <intelblocks/pcr.h>
 #include <intelpch/lockdown.h>
+#include <soc/pcr_ids.h>
 #include <soc/pm.h>
 #include <stdint.h>
 
+/* PCR PSTH Control Register */
+#define PCR_PSTH_CTRLREG		0x1d00
+#define   PSTH_CTRLREG_IOSFPTCGE	(1 << 2)
+
 static void pmc_lockdown_cfg(int chipset_lockdown)
 {
 	uint8_t *pmcbase = pmc_mmio_regs();
@@ -32,8 +38,19 @@ static void pmc_lockdown_cfg(int chipset_lockdown)
 	}
 }
 
+static void pch_lockdown_cfg(void)
+{
+	if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
+		return;
+
+	/* Enable IOSF Primary Trunk Clock Gating */
+	pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
+}
+
 void soc_lockdown_config(int chipset_lockdown)
 {
 	/* PMC lock down configuration */
 	pmc_lockdown_cfg(chipset_lockdown);
+	/* PCH lock down configuration */
+	pch_lockdown_cfg();
 }