- Update e7501 northbridge.c to work in the new structure.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
8abb054c0e
commit
720a8f57ef
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@ -9,113 +9,8 @@
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#include <string.h>
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#include <bitops.h>
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#include "chip.h"
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#if 0
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struct mem_range *sizeram(void)
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{
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static struct mem_range mem[4];
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/* the units of tolm are 64 KB */
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/* the units of drb16 are 64 MB */
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uint16_t tolm, remapbase, remaplimit, drb16;
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uint16_t tolm_r, remapbase_r, remaplimit_r;
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uint8_t drb;
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int remap_high;
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device_t dev;
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dev = dev_find_slot(0, 0); // d0f0
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if (!dev) {
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printk_err("Cannot find PCI: 0:0\n");
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return 0;
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}
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/* Calculate and report the top of low memory and
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* any remapping.
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*/
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/* Test if the remap memory high option is set */
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remap_high = 0;
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// if(get_option(&remap_high, "remap_memory_high")){
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// remap_high = 0;
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// }
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printk_debug("remap_high is %d\n", remap_high);
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/* get out the value of the highest DRB. This tells the end of
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* physical memory. The units are ticks of 64 MB i.e. 1 means
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* 64 MB.
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*/
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drb = pci_read_config8(dev, 0x67);
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drb16 = (uint16_t)drb;
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if(remap_high && (drb16 > 0x08)) {
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/* We only come here if we have at least 512MB of memory,
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* so it is safe to hard code tolm.
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* 0x2000 means 512MB
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*/
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tolm = 0x2000;
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/* i.e 0x40 * 0x40 is 0x1000 which is 4 GB */
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if(drb16 > 0x0040) {
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/* There is more than 4GB of memory put
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* the remap window at the end of ram.
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*/
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remapbase = drb16;
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remaplimit = remapbase + 0x38;
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}
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else {
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remapbase = 0x0040;
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remaplimit = remapbase + (drb16-8);
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}
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}
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else {
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tolm = (uint16_t)((dev_root.resource[1].base >> 16)&0x0f800);
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if((tolm>>8) >= (drb16<<2)) {
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tolm = (drb16<<10);
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remapbase = 0x3ff;
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remaplimit = 0;
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}
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else {
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remapbase = drb16;
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remaplimit = remapbase + ((0x0040-(tolm>>10))-1);
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}
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}
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/* Write the ram configruation registers,
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* preserving the reserved bits.
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*/
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tolm_r = pci_read_config16(dev, 0xc4);
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tolm |= (tolm_r & 0x7ff);
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pci_write_config16(dev, 0xc4, tolm);
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remapbase_r = pci_read_config16(dev, 0xc6);
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remapbase |= (remapbase_r & 0xfc00);
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pci_write_config16(dev, 0xc6, remapbase);
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remaplimit_r = pci_read_config16(dev, 0xc8);
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remaplimit |= (remaplimit_r & 0xfc00);
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pci_write_config16(dev, 0xc8, remaplimit);
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#if 0
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printk_debug("mem info tolm = %x, drb = %x, pci_memory_base = %x, remap = %x-%x\n",tolm,drb,pci_memory_base,remapbase,remaplimit);
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#endif
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mem[0].basek = 0;
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mem[0].sizek = 640;
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mem[1].basek = 768;
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/* Convert size in 64K bytes to size in K bytes */
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mem[1].sizek = (tolm << 6) - mem[1].basek;
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mem[2].basek = 0;
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mem[2].sizek = 0;
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if ((drb << 16) > (tolm << 6)) {
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/* We don't need to consider the remap window
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* here because we put it immediately after the
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* rest of ram.
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* All we must do is calculate the amount
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* of unused memory and report it at 4GB.
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*/
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mem[2].basek = 4096*1024;
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mem[2].sizek = (drb << 16) - (tolm << 6);
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}
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mem[3].basek = 0;
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mem[3].sizek = 0;
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return mem;
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}
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#endif
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#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
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#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
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static void pci_domain_read_resources(device_t dev)
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{
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@ -130,21 +25,12 @@ static void pci_domain_read_resources(device_t dev)
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compute_allocate_resource(&dev->link[0], resource,
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IORESOURCE_IO, IORESOURCE_IO);
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/* Initialize the system wide prefetchable memory resources constraints */
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resource = new_resource(dev, 1);
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resource->limit = 0xfcffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
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compute_allocate_resource(&dev->link[0], resource,
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IORESOURCE_MEM | IORESOURCE_PREFETCH,
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IORESOURCE_MEM | IORESOURCE_PREFETCH);
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(dev, 2);
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resource->limit = 0xfcffffffffULL;
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resource = new_resource(dev, 1);
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resource->limit = 0xffffffffULL;
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resource->flags = IORESOURCE_MEM;
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compute_allocate_resource(&dev->link[0], resource,
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IORESOURCE_MEM | IORESOURCE_PREFETCH,
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IORESOURCE_MEM);
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IORESOURCE_MEM, IORESOURCE_MEM);
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}
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static void ram_resource(device_t dev, unsigned long index,
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@ -164,72 +50,14 @@ static void ram_resource(device_t dev, unsigned long index,
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static void pci_domain_set_resources(device_t dev)
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{
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struct resource *io, *mem1, *mem2;
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struct resource *resource, *last;
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unsigned long mmio_basek;
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device_t mc_dev;
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uint32_t pci_tolm;
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int idx;
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uint8_t drb;
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unsigned basek, sizek;
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device_t dev_memctrl;
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#if 0
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/* Place the IO devices somewhere safe */
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io = find_resource(dev, 0);
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io->base = DEVICE_IO_START;
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#endif
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#if 1
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/* Now reallocate the pci resources memory with the
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* highest addresses I can manage.
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*/
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mem1 = find_resource(dev, 1);
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mem2 = find_resource(dev, 2);
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#if 1
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printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem1->base, mem1->limit, mem1->size, mem1->align);
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printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem2->base, mem2->limit, mem2->size, mem2->align);
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#endif
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/* See if both resources have roughly the same limits */
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if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
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((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
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{
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/* If so place the one with the most stringent alignment first
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*/
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if (mem2->align > mem1->align) {
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struct resource *tmp;
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tmp = mem1;
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mem1 = mem2;
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mem2 = tmp;
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}
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/* Now place the memory as high up as it will go */
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mem2->base = resource_max(mem2);
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mem1->limit = mem2->base - 1;
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mem1->base = resource_max(mem1);
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}
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else {
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/* Place the resources as high up as they will go */
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mem2->base = resource_max(mem2);
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mem1->base = resource_max(mem1);
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}
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#if 1
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printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem1->base, mem1->limit, mem1->size, mem1->align);
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printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
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mem2->base, mem2->limit, mem2->size, mem2->align);
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#endif
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#endif
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pci_tolm = 0xffffffffUL;
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last = &dev->resource[dev->resources];
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for(resource = &dev->resource[0]; resource < last; resource++)
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{
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#if 1
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resource->flags |= IORESOURCE_ASSIGNED;
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resource->flags &= ~IORESOURCE_STORED;
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#endif
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compute_allocate_resource(&dev->link[0], resource,
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BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
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@ -243,43 +71,77 @@ static void pci_domain_set_resources(device_t dev)
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}
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}
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#warning "FIXME handle interleaved nodes"
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mmio_basek = pci_tolm >> 10;
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/* Round mmio_basek to something the processor can support */
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mmio_basek &= ~((1 << 6) -1);
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mc_dev = dev->link[0].children;
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if (mc_dev) {
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/* Figure out which areas are/should be occupied by RAM.
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* This is all computed in kilobytes and converted to/from
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* the memory controller right at the edges.
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* Having different variables in different units is
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* too confusing to get right. Kilobytes are good up to
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* 4 Terabytes of RAM...
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*/
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uint16_t tolm_r, remapbase_r, remaplimit_r;
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unsigned long tomk, tolmk;
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unsigned long remapbasek, remaplimitk;
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int idx;
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#if 1
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#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
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/* Round the mmio hold to 64M */
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mmio_basek &= ~((64*1024) - 1);
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#endif
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/* Get the value of the highest DRB. This tells the end of
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* the physical memory. The units are ticks of 64MB
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* i.e. 1 means 64MB.
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*/
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tomk = ((unsigned long)pci_read_config8(mc_dev, 0x67)) << 16;
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/* Compute the top of Low memory */
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tolmk = pci_tolm >> 10;
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if (tolmk >= tomk) {
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/* The PCI hole does not overlap memory
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* we won't use the remap window.
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*/
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tolmk = tomk;
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remapbasek = 0x3ff << 16;
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remaplimitk = 0 << 16;
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}
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else {
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/* The PCI memory hole overlaps memory
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* setup the remap window.
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*/
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/* Find the bottom of the remap window
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* is it above 4G?
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*/
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remapbasek = 4*1024*1024;
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if (tomk > remapbasek) {
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remapbasek = tomk;
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}
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/* Find the limit of the remap window */
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remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
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}
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/* Write the ram configuration registers,
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* preserving the reserved bits.
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*/
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tolm_r = pci_read_config16(mc_dev, 0xc4);
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tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
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pci_write_config16(mc_dev, 0xc4, tolm_r);
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dev_memctrl = dev_find_slot(0, 0); // d0f0
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drb = pci_read_config8(dev_memctrl, 0x67);
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idx = 10;
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basek = 0;
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sizek = 640;
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ram_resource(dev, idx++, basek, sizek);
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basek = 768;
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sizek = mmio_basek - basek;
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ram_resource(dev, idx++, basek, sizek);
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if ((drb << 16) > mmio_basek) {
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/* We don't need to consider the remap window
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* here because we put it immediately after the
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* rest of ram.
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* All we must do is calculate the amount
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* of unused memory and report it at 4GB.
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*/
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basek = 4096*1024;
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sizek = (drb << 16) - mmio_basek;
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ram_resource(dev, idx++, basek, sizek);
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remapbase_r = pci_read_config16(mc_dev, 0xc6);
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remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
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pci_write_config16(mc_dev, 0xc6, remapbase_r);
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remaplimit_r = pci_read_config16(mc_dev, 0xc8);
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remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
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pci_write_config16(mc_dev, 0xc8, rempaplimit_r);
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/* Report the memory regions */
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idx = 10;
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ram_resource(dev, idx++, 0, 640);
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ram_resource(dev, idx++, 768, tolmk - 768);
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if (tomk > 4*1024*1024) {
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ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
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}
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if (remaplimitk >= remapbasek) {
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ram_resource(dev, idx++, ramapbasek,
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(reamplimitk + 64*1024) = remapbasek);
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}
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}
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assign_resources(&dev->link[0]);
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assign_resources(&dev->link[0]);
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}
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static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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@ -296,56 +158,6 @@ static struct device_operations pci_domain_ops = {
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.scan_bus = pci_domain_scan_bus,
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};
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static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
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{
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struct bus *cpu_bus;
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unsigned reg;
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int i;
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/* Find which cpus are present */
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cpu_bus = &dev->link[0];
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for(i = 0; i < 7; i+=6) {
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device_t dev, cpu;
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struct device_path cpu_path;
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#if 0
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//How to identify Intel CPU
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/* Find the cpu's memory controller */
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dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
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#endif
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/* Build the cpu device path */
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cpu_path.type = DEVICE_PATH_APIC;
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cpu_path.u.apic.apic_id = i;
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/* See if I can find the cpu */
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cpu = find_dev_path(cpu_bus, &cpu_path);
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#if 0
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/* Enable the cpu if I have the processor */
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if (dev && dev->enabled) {
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if (!cpu) {
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cpu = alloc_dev(cpu_bus, &cpu_path);
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}
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if (cpu) {
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cpu->enabled = 1;
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}
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}
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/* Disable the cpu if I don't have the processor */
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if (cpu && (!dev || !dev->enabled)) {
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cpu->enabled = 0;
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}
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#else
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cpu->enabled = 1;
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#endif
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/* Report what I have done */
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if (cpu) {
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printk_debug("CPU: %s %s\n",
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dev_path(cpu), cpu->enabled?"enabled":"disabled");
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}
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}
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return max;
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}
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static void cpu_bus_init(device_t dev)
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{
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initialize_cpus(&dev->link[0]);
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@ -360,7 +172,7 @@ static struct device_operations cpu_bus_ops = {
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.set_resources = cpu_bus_noop,
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.enable_resources = cpu_bus_noop,
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.init = cpu_bus_init,
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.scan_bus = cpu_bus_scan,
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.scan_bus = cpu_bus_noop,
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};
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static void enable_dev(struct device *dev)
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