i2c mux support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu
parent
57b6786168
commit
7213d0f513
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@ -5,3 +5,4 @@ object pci_device.o
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object pnp_device.o
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object pnp_device.o
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object hypertransport.o
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object hypertransport.o
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object pci_ops.o
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object pci_ops.o
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object smbus_ops.o
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@ -0,0 +1,93 @@
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#include <console/console.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/path.h>
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#include <device/smbus.h>
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struct bus *get_pbus_smbus(device_t dev)
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{
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struct bus *pbus = dev->bus;
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while(pbus && pbus->dev && !ops_smbus_bus(pbus)) {
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pbus = pbus->dev->bus;
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}
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if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_smbus_bus) {
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printk_alert("%s Cannot find smbus bus operations", dev_path(dev));
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die("");
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for(;;);
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}
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return pbus;
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}
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/*multi level i2c MUX??? may need to find the first i2c device and then set link down to current dev
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1 store get_pbus_smbus list link
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2 reverse the link and call set link */
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int smbus_set_link(device_t dev)
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{
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struct bus *pbus_a[4]; // 4 level mux only. Enough?
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struct bus *pbus = dev->bus;
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int pbus_num=0;
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int i;
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while(pbus && pbus->dev && (pbus->dev->path.type==DEVICE_PATH_I2C)) {
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pbus_a[pbus_num++] = pbus;
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pbus = pbus->dev->bus;
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}
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// printk_info("smbus_set_link: ");
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for(i=pbus_num-1; i>=0; i--) {
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// printk_info(" %s[%d] -> ", dev_path(pbus_a[i]->dev), pbus_a[i]->link);
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if(ops_smbus_bus(get_pbus_smbus(pbus_a[i]->dev))) {
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if(pbus_a[i]->dev->ops && pbus_a[i]->dev->ops->set_link)
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pbus_a[i]->dev->ops->set_link(pbus_a[i]->dev, pbus_a[i]->link);
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}
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}
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// printk_info(" %s\n", dev_path(dev));
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return pbus_num;
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}
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int smbus_quick_read(device_t dev)
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{
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return ops_smbus_bus(get_pbus_smbus(dev))->quick_read(dev);
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}
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int smbus_quick_write(device_t dev)
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{
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return ops_smbus_bus(get_pbus_smbus(dev))->quick_write(dev);
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}
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int smbus_recv_byte(device_t dev)
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{
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return ops_smbus_bus(get_pbus_smbus(dev))->recv_byte(dev);
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}
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int smbus_send_byte(device_t dev, uint8_t byte)
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{
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return ops_smbus_bus(get_pbus_smbus(dev))->send_byte(dev, byte);
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}
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int smbus_read_byte(device_t dev, uint8_t addr)
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{
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return ops_smbus_bus(get_pbus_smbus(dev))->read_byte(dev, addr);
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}
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int smbus_write_byte(device_t dev, uint8_t addr, uint8_t val)
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{
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return ops_smbus_bus(get_pbus_smbus(dev))->write_byte(dev, addr, val);
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}
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int smbus_read_word(device_t dev, uint8_t addr)
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{
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return ops_smbus_bus(get_pbus_smbus(dev))->read_word(dev, addr);
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}
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int smbus_write_word(device_t dev, uint8_t addr, uint16_t val)
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{
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return ops_smbus_bus(get_pbus_smbus(dev))->write_word(dev, addr, val);
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}
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int smbus_process_call(device_t dev, uint8_t cmd, uint16_t data)
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{
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return ops_smbus_bus(get_pbus_smbus(dev))->process_call(dev, cmd, data);
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}
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int smbus_block_read(device_t dev, uint8_t cmd, uint8_t bytes, uint8_t *buffer)
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{
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return ops_smbus_bus(get_pbus_smbus(dev))->block_read(dev, cmd, bytes, buffer);
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}
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int smbus_block_write(device_t dev, uint8_t cmd, uint8_t bytes, const uint8_t *buffer)
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{
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return ops_smbus_bus(get_pbus_smbus(dev))->block_write(dev, cmd, bytes, buffer);
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}
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@ -1,5 +1,6 @@
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#include <console/console.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/smbus.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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@ -46,7 +47,7 @@ static void print_pci_regs_all(void)
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if(!dev->enabled) {
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if(!dev->enabled) {
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continue;
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continue;
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}
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}
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printk_debug("\n%02x:%02x:%02x aka %s",i,j,k, dev_path(dev));
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printk_debug("\n%02x:%02x:%02x aka %s",i,j,k, dev_path(dev));
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print_pci_regs(dev);
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print_pci_regs(dev);
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}
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}
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}
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}
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@ -56,28 +57,72 @@ static void print_pci_regs_all(void)
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static void print_msr()
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static void print_msr()
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{
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{
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msr_t msr;
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msr_t msr;
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unsigned index;
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unsigned index;
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unsigned eax, ebx, ecx, edx;
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unsigned eax, ebx, ecx, edx;
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index = 0x80000007;
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index = 0x80000007;
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printk_debug("calling cpuid 0x%08x\n", index);
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printk_debug("calling cpuid 0x%08x\n", index);
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asm volatile(
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asm volatile(
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"cpuid"
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"cpuid"
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
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: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
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: "a" (index)
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: "a" (index)
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);
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);
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printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
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printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
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index, eax, ebx, ecx, edx);
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index, eax, ebx, ecx, edx);
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if (edx & (3 << 1)) {
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if (edx & (3 << 1)) {
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index = 0xC0010042;
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index = 0xC0010042;
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printk_debug("Reading msr: 0x%08x\n", index);
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printk_debug("Reading msr: 0x%08x\n", index);
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msr = rdmsr(index);
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msr = rdmsr(index);
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printk_debug("msr[0x%08x]: 0x%08x%08x\n",
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printk_debug("msr[0x%08x]: 0x%08x%08x\n",
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index, msr.hi, msr.hi);
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index, msr.hi, msr.hi);
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}
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}
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}
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}
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static void print_smbus_regs(struct device *dev)
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{
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int j;
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printk_debug("smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link );
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printk_debug("%s", dev_path(dev));
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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printk_debug("\r\n%02x: ", j);
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}
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status = smbus_read_byte(dev, j);
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if (status < 0) {
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printk_debug("bad device status= %08x\r\n", status);
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break;
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}
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byte = status & 0xff;
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printk_debug("%02x ", byte);
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}
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printk_debug("\r\n");
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}
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static void print_smbus_regs_all(struct device *dev)
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{
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struct device *child;
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int i;
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if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
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{
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// Here don't need to call smbus_set_link, because we scan it from top to down
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if( dev->bus->dev->path.type == DEVICE_PATH_I2C) { // it's under i2c MUX so set mux at first
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if(ops_smbus_bus(get_pbus_smbus(dev->bus->dev))) {
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if(dev->bus->dev->ops && dev->bus->dev->ops->set_link)
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dev->bus->dev->ops->set_link(dev->bus->dev, dev->bus->link);
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}
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}
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if(ops_smbus_bus(get_pbus_smbus(dev))) print_smbus_regs(dev);
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}
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for(i=0; i< dev->links; i++) {
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for (child = dev->link[i].children; child; child = child->sibling) {
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print_smbus_regs_all(child);
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}
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}
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}
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static void debug_init(device_t dev)
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static void debug_init(device_t dev)
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{
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{
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device_t parent;
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device_t parent;
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@ -103,6 +148,9 @@ static void debug_init(device_t dev)
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case 3:
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case 3:
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print_msr();
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print_msr();
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break;
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break;
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case 4:
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print_smbus_regs_all(&dev_root);
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break;
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}
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}
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}
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}
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@ -0,0 +1,2 @@
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config chip.h
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object adm1026.o
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@ -0,0 +1,68 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/smbus.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <part/hard_reset.h>
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#include <cpu/x86/msr.h>
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#include "chip.h"
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#define ADM1026_DEVICE 0x2c /* 0x2e or 0x2d */
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#define ADM1026_REG_CONFIG1 0x00
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#define CFG1_MONITOR 0x01
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#define CFG1_INT_ENABLE 0x02
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#define CFG1_INT_CLEAR 0x04
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#define CFG1_AIN8_9 0x08
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#define CFG1_THERM_HOT 0x10
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#define CFT1_DAC_AFC 0x20
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#define CFG1_PWM_AFC 0x40
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#define CFG1_RESET 0x80
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#define ADM1026_REG_CONFIG2 0x01
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#define ADM1026_REG_CONFIG3 0x07
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static void adm1026_init(device_t dev)
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{
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if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
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{
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if(ops_smbus_bus(get_pbus_smbus(dev))) {
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if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux
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adm1026_enable_monitoring(dev);
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}
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}
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}
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static void adm1026_enable_monitoring(device_t dev)
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{
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int result;
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result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
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result = (result | CFG1_MONITOR) & ~(CFG1_INT_CLEAR | CFG1_RESET);
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result = smbus_write_byte(dev, ADM1026_REG_CONFIG1, result);
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result = smbus_read_byte(dev, ADM1026_REG_CONFIG1);
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if (!(result & CFG1_MONITOR)) {
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printk_debug("ADM1026: monitoring would not enable");
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}
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}
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static void adm1026_noop(device_t dummy)
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{
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}
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static struct device_operations adm1026_operations = {
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.read_resources = adm1026_noop,
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.set_resources = adm1026_noop,
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.enable_resources = adm1026_noop,
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.init = adm1026_init,
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};
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static void enable_dev(struct device *dev)
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{
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dev->ops = &adm1026_operations;
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}
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struct chip_operations drivers_i2c_adm1026_ops = {
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CHIP_NAME("adm1026")
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.enable_dev = enable_dev,
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};
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@ -0,0 +1,4 @@
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extern struct chip_operations drivers_i2c_adm1026_ops;
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struct drivers_i2c_adm1026_config {
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};
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@ -0,0 +1,2 @@
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config chip.h
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object adm1027.o
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@ -0,0 +1,72 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <device/smbus.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <part/hard_reset.h>
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#include <cpu/x86/msr.h>
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#include "chip.h"
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#define ADM1027_REG_CONFIG1 0x40
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#define CFG1_STRT 0x01
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#define CFG1_LOCK 0x02
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#define CFG1_RDY 0x04
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#define CFG1_FSPD 0x08
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#define CFG1_VXI 0x10
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#define CFT1_FSPDIS 0x20
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#define CFG1_TODIS 0x40
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#define CFG1_VCC 0x80
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#define ADM1027_REG_CONFIG2 0x73
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#define ADM1027_REG_CONFIG3 0x78
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static void adm1027_enable_monitoring(device_t dev)
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{
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int result;
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result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
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if(!(result & CFG1_RDY) ) {
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printk_debug("ADM1027: monitoring not ready");
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return;
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}
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result = (result | CFG1_STRT);
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result = smbus_write_byte(dev, ADM1027_REG_CONFIG1, result);
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result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
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if (!(result & CFG1_STRT)) {
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printk_debug("ADM1027: monitoring would not enable");
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}
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}
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static void adm1027_init(device_t dev)
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{
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if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
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{
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if(ops_smbus_bus(get_pbus_smbus(dev))) {
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if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux
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adm1027_enable_monitoring(dev);
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}
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}
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}
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static void adm1027_noop(device_t dummy)
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{
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}
|
||||||
|
|
||||||
|
static struct device_operations adm1027_operations = {
|
||||||
|
.read_resources = adm1027_noop,
|
||||||
|
.set_resources = adm1027_noop,
|
||||||
|
.enable_resources = adm1027_noop,
|
||||||
|
.init = adm1027_init,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void enable_dev(struct device *dev)
|
||||||
|
{
|
||||||
|
dev->ops = &adm1027_operations;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct chip_operations drivers_i2c_adm1027_ops = {
|
||||||
|
CHIP_NAME("adm1027")
|
||||||
|
.enable_dev = enable_dev,
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,4 @@
|
||||||
|
extern struct chip_operations drivers_i2c_adm1027_ops;
|
||||||
|
|
||||||
|
struct drivers_i2c_adm1027_config {
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,2 @@
|
||||||
|
config chip.h
|
||||||
|
object i2cmux.o
|
||||||
|
|
@ -0,0 +1,4 @@
|
||||||
|
extern struct chip_operations drivers_i2c_i2cmux_ops;
|
||||||
|
|
||||||
|
struct drivers_i2c_i2cmux_config {
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,44 @@
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <device/smbus.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <device/pci_ops.h>
|
||||||
|
#include <cpu/x86/msr.h>
|
||||||
|
#include "chip.h"
|
||||||
|
|
||||||
|
static void i2cmux_set_link(device_t dev, unsigned int link)
|
||||||
|
{
|
||||||
|
if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
|
||||||
|
{
|
||||||
|
if(ops_smbus_bus(get_pbus_smbus(dev))) {
|
||||||
|
smbus_write_byte(dev, 0x01, 1<<link); // output value
|
||||||
|
smbus_write_byte(dev, 0x03, 0); // all output
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
static void i2cmux_noop(device_t dummy)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct device_operations i2cmux_operations = {
|
||||||
|
.read_resources = i2cmux_noop,
|
||||||
|
.set_resources = i2cmux_noop,
|
||||||
|
.enable_resources = i2cmux_noop,
|
||||||
|
.init = i2cmux_noop,
|
||||||
|
.scan_bus = scan_static_bus,
|
||||||
|
.set_link = i2cmux_set_link,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void enable_dev(struct device *dev)
|
||||||
|
{
|
||||||
|
if(dev->links>0)
|
||||||
|
dev->ops = &i2cmux_operations;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct chip_operations drivers_i2c_i2cmux_ops = {
|
||||||
|
CHIP_NAME("i2cmux")
|
||||||
|
.enable_dev = enable_dev,
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,2 @@
|
||||||
|
config chip.h
|
||||||
|
object lm63.o
|
||||||
|
|
@ -0,0 +1,4 @@
|
||||||
|
extern struct chip_operations drivers_i2c_lm63_ops;
|
||||||
|
|
||||||
|
struct drivers_i2c_lm63_config {
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,46 @@
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <device/smbus.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <device/pci_ops.h>
|
||||||
|
#include <cpu/x86/msr.h>
|
||||||
|
#include "chip.h"
|
||||||
|
|
||||||
|
|
||||||
|
static void lm63_init(device_t dev)
|
||||||
|
{
|
||||||
|
int result;
|
||||||
|
if (dev->enabled && dev->path.type == DEVICE_PATH_I2C)
|
||||||
|
{
|
||||||
|
if(ops_smbus_bus(get_pbus_smbus(dev))) {
|
||||||
|
if( dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux
|
||||||
|
result = smbus_read_byte(dev, 0x03);
|
||||||
|
// result &= ~0x04;
|
||||||
|
result |= 0x04;
|
||||||
|
smbus_write_byte(dev, 0x03, result & 0xff); // config lm63
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
static void lm63_noop(device_t dummy)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct device_operations lm63_operations = {
|
||||||
|
.read_resources = lm63_noop,
|
||||||
|
.set_resources = lm63_noop,
|
||||||
|
.enable_resources = lm63_noop,
|
||||||
|
.init = lm63_init,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void enable_dev(struct device *dev)
|
||||||
|
{
|
||||||
|
dev->ops = &lm63_operations;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct chip_operations drivers_i2c_lm63_ops = {
|
||||||
|
CHIP_NAME("lm63")
|
||||||
|
.enable_dev = enable_dev,
|
||||||
|
};
|
||||||
|
|
@ -33,6 +33,7 @@ struct device_operations {
|
||||||
void (*init)(device_t dev);
|
void (*init)(device_t dev);
|
||||||
unsigned int (*scan_bus)(device_t bus, unsigned int max);
|
unsigned int (*scan_bus)(device_t bus, unsigned int max);
|
||||||
void (*enable)(device_t dev);
|
void (*enable)(device_t dev);
|
||||||
|
void (*set_link)(device_t dev, unsigned int link);
|
||||||
const struct pci_operations *ops_pci;
|
const struct pci_operations *ops_pci;
|
||||||
const struct smbus_bus_operations *ops_smbus_bus;
|
const struct smbus_bus_operations *ops_smbus_bus;
|
||||||
const struct pci_bus_operations *ops_pci_bus;
|
const struct pci_bus_operations *ops_pci_bus;
|
||||||
|
|
@ -50,7 +51,7 @@ struct bus {
|
||||||
};
|
};
|
||||||
|
|
||||||
#define MAX_RESOURCES 12
|
#define MAX_RESOURCES 12
|
||||||
#define MAX_LINKS 4
|
#define MAX_LINKS 8
|
||||||
/*
|
/*
|
||||||
* There is one device structure for each slot-number/function-number
|
* There is one device structure for each slot-number/function-number
|
||||||
* combination:
|
* combination:
|
||||||
|
|
|
||||||
|
|
@ -21,50 +21,29 @@ struct smbus_bus_operations {
|
||||||
int (*block_write) (device_t dev, uint8_t cmd, uint8_t bytes, const uint8_t *buffer);
|
int (*block_write) (device_t dev, uint8_t cmd, uint8_t bytes, const uint8_t *buffer);
|
||||||
};
|
};
|
||||||
|
|
||||||
static inline int smbus_quick_read(device_t dev)
|
static inline const struct smbus_bus_operations *ops_smbus_bus(struct bus *bus)
|
||||||
{
|
{
|
||||||
return dev->bus->dev->ops->ops_smbus_bus->quick_read(dev);
|
const struct smbus_bus_operations *bops;
|
||||||
}
|
bops = 0;
|
||||||
static inline int smbus_quick_write(device_t dev)
|
if (bus && bus->dev && bus->dev->ops) {
|
||||||
{
|
bops = bus->dev->ops->ops_smbus_bus;
|
||||||
return dev->bus->dev->ops->ops_smbus_bus->quick_write(dev);
|
}
|
||||||
}
|
return bops;
|
||||||
static inline int smbus_recv_byte(device_t dev)
|
|
||||||
{
|
|
||||||
return dev->bus->dev->ops->ops_smbus_bus->recv_byte(dev);
|
|
||||||
}
|
|
||||||
static inline int smbus_send_byte(device_t dev, uint8_t byte)
|
|
||||||
{
|
|
||||||
return dev->bus->dev->ops->ops_smbus_bus->send_byte(dev, byte);
|
|
||||||
}
|
|
||||||
static inline int smbus_read_byte(device_t dev, uint8_t addr)
|
|
||||||
{
|
|
||||||
return dev->bus->dev->ops->ops_smbus_bus->read_byte(dev, addr);
|
|
||||||
}
|
|
||||||
static inline int smbus_write_byte(device_t dev, uint8_t addr, uint8_t val)
|
|
||||||
{
|
|
||||||
return dev->bus->dev->ops->ops_smbus_bus->write_byte(dev, addr, val);
|
|
||||||
}
|
|
||||||
static inline int smbus_read_word(device_t dev, uint8_t addr)
|
|
||||||
{
|
|
||||||
return dev->bus->dev->ops->ops_smbus_bus->read_word(dev, addr);
|
|
||||||
}
|
|
||||||
static inline int smbus_write_word(device_t dev, uint8_t addr, uint16_t val)
|
|
||||||
{
|
|
||||||
return dev->bus->dev->ops->ops_smbus_bus->write_word(dev, addr, val);
|
|
||||||
}
|
|
||||||
static inline int smbus_process_call(device_t dev, uint8_t cmd, uint16_t data)
|
|
||||||
{
|
|
||||||
return dev->bus->dev->ops->ops_smbus_bus->process_call(dev, cmd, data);
|
|
||||||
}
|
|
||||||
static inline int smbus_block_read(device_t dev, uint8_t cmd, uint8_t bytes, uint8_t *buffer)
|
|
||||||
{
|
|
||||||
return dev->bus->dev->ops->ops_smbus_bus->block_read(dev, cmd, bytes, buffer);
|
|
||||||
}
|
|
||||||
static inline int smbus_block_write(device_t dev, uint8_t cmd, uint8_t bytes, const uint8_t *buffer)
|
|
||||||
{
|
|
||||||
return dev->bus->dev->ops->ops_smbus_bus->block_write(dev, cmd, bytes, buffer);
|
|
||||||
}
|
}
|
||||||
|
struct bus *get_pbus_smbus(device_t dev);
|
||||||
|
int smbus_set_link(device_t dev);
|
||||||
|
|
||||||
|
int smbus_quick_read(device_t dev);
|
||||||
|
int smbus_quick_write(device_t dev);
|
||||||
|
int smbus_recv_byte(device_t dev);
|
||||||
|
int smbus_send_byte(device_t dev, uint8_t byte);
|
||||||
|
int smbus_read_byte(device_t dev, uint8_t addr);
|
||||||
|
int smbus_write_byte(device_t dev, uint8_t addr, uint8_t val);
|
||||||
|
int smbus_read_word(device_t dev, uint8_t addr);
|
||||||
|
int smbus_write_word(device_t dev, uint8_t addr, uint16_t val);
|
||||||
|
int smbus_process_call(device_t dev, uint8_t cmd, uint16_t data);
|
||||||
|
int smbus_block_read(device_t dev, uint8_t cmd, uint8_t bytes, uint8_t *buffer);
|
||||||
|
int smbus_block_write(device_t dev, uint8_t cmd, uint8_t bytes, const uint8_t *buffer);
|
||||||
|
|
||||||
|
|
||||||
#endif /* DEVICE_SMBUS_H */
|
#endif /* DEVICE_SMBUS_H */
|
||||||
|
|
|
||||||
|
|
@ -181,7 +181,7 @@ chip northbridge/amd/amdk8/root_complex
|
||||||
io 0x60 = 0x3f8
|
io 0x60 = 0x3f8
|
||||||
irq 0x70 = 4
|
irq 0x70 = 4
|
||||||
end
|
end
|
||||||
device pnp 2e.3 off # Com2
|
device pnp 2e.3 on # Com2
|
||||||
io 0x60 = 0x2f8
|
io 0x60 = 0x2f8
|
||||||
irq 0x70 = 3
|
irq 0x70 = 3
|
||||||
end
|
end
|
||||||
|
|
@ -195,8 +195,8 @@ chip northbridge/amd/amdk8/root_complex
|
||||||
io 0x60 = 0x100
|
io 0x60 = 0x100
|
||||||
end
|
end
|
||||||
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||||
io 0x60 = 0x201
|
io 0x60 = 0x220
|
||||||
io 0x62 = 0x330
|
io 0x62 = 0x300
|
||||||
irq 0x70 = 9
|
irq 0x70 = 9
|
||||||
end
|
end
|
||||||
device pnp 2e.8 off end # GPIO2
|
device pnp 2e.8 off end # GPIO2
|
||||||
|
|
@ -210,7 +210,32 @@ chip northbridge/amd/amdk8/root_complex
|
||||||
end
|
end
|
||||||
device pci 1.1 on end
|
device pci 1.1 on end
|
||||||
device pci 1.2 on end
|
device pci 1.2 on end
|
||||||
device pci 1.3 on end
|
device pci 1.3 on
|
||||||
|
chip drivers/generic/generic #dimm 0-0-0
|
||||||
|
device i2c 50 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 0-0-1
|
||||||
|
device i2c 51 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 0-1-0
|
||||||
|
device i2c 52 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 0-1-1
|
||||||
|
device i2c 53 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 1-0-0
|
||||||
|
device i2c 54 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 1-0-1
|
||||||
|
device i2c 55 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 1-1-0
|
||||||
|
device i2c 56 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 1-1-1
|
||||||
|
device i2c 57 on end
|
||||||
|
end
|
||||||
|
end # acpi
|
||||||
device pci 1.5 on end
|
device pci 1.5 on end
|
||||||
device pci 1.6 off end
|
device pci 1.6 off end
|
||||||
register "ide0_enable" = "1"
|
register "ide0_enable" = "1"
|
||||||
|
|
@ -221,12 +246,12 @@ chip northbridge/amd/amdk8/root_complex
|
||||||
device pci 18.1 on end
|
device pci 18.1 on end
|
||||||
device pci 18.2 on end
|
device pci 18.2 on end
|
||||||
device pci 18.3 on
|
device pci 18.3 on
|
||||||
# chip drivers/generic/debug
|
# chip drivers/generic/debug
|
||||||
# device pnp 1.0 on end
|
# device pnp 1.0 on end
|
||||||
# device pnp 1.1 off end
|
# device pnp 1.1 off end
|
||||||
# device pnp 1.2 off end
|
# device pnp 1.2 off end
|
||||||
# device pnp 1.3 on end
|
# device pnp 1.3 on end
|
||||||
# end
|
# end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
@ -248,11 +273,11 @@ chip northbridge/amd/amdk8/root_complex
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
chip drivers/generic/debug
|
# chip drivers/generic/debug
|
||||||
device pnp 0.0 on end
|
# device pnp 0.0 on end
|
||||||
device pnp 0.1 off end
|
# device pnp 0.1 off end
|
||||||
device pnp 0.2 off end
|
# device pnp 0.2 off end
|
||||||
device pnp 0.3 on end
|
# device pnp 0.3 on end
|
||||||
end
|
# end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -152,30 +152,30 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||||
static void main(unsigned long bist)
|
static void main(unsigned long bist)
|
||||||
{
|
{
|
||||||
static const struct mem_controller cpu[] = {
|
static const struct mem_controller cpu[] = {
|
||||||
#if FIRST_CPU
|
#if FIRST_CPU
|
||||||
{
|
{
|
||||||
.node_id = 0,
|
.node_id = 0,
|
||||||
.f0 = PCI_DEV(0, 0x18, 0),
|
.f0 = PCI_DEV(0, 0x18, 0),
|
||||||
.f1 = PCI_DEV(0, 0x18, 1),
|
.f1 = PCI_DEV(0, 0x18, 1),
|
||||||
.f2 = PCI_DEV(0, 0x18, 2),
|
.f2 = PCI_DEV(0, 0x18, 2),
|
||||||
.f3 = PCI_DEV(0, 0x18, 3),
|
.f3 = PCI_DEV(0, 0x18, 3),
|
||||||
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
|
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
|
||||||
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
|
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
#if SECOND_CPU
|
#if SECOND_CPU
|
||||||
{
|
{
|
||||||
.node_id = 1,
|
.node_id = 1,
|
||||||
.f0 = PCI_DEV(0, 0x19, 0),
|
.f0 = PCI_DEV(0, 0x19, 0),
|
||||||
.f1 = PCI_DEV(0, 0x19, 1),
|
.f1 = PCI_DEV(0, 0x19, 1),
|
||||||
.f2 = PCI_DEV(0, 0x19, 2),
|
.f2 = PCI_DEV(0, 0x19, 2),
|
||||||
.f3 = PCI_DEV(0, 0x19, 3),
|
.f3 = PCI_DEV(0, 0x19, 3),
|
||||||
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
|
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
|
||||||
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
|
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
|
||||||
},
|
},
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
#if 1
|
#if 1
|
||||||
static const struct ht_chain ht_c[] = {
|
static const struct ht_chain ht_c[] = {
|
||||||
|
|
@ -245,33 +245,28 @@ static void main(unsigned long bist)
|
||||||
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
dump_pci_devices();
|
dump_pci_devices();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/* Check all of memory */
|
||||||
#if 0
|
#if 0
|
||||||
dump_pci_device(PCI_DEV(0, 0x18, 1));
|
msr_t msr;
|
||||||
|
msr = rdmsr(TOP_MEM2);
|
||||||
|
print_debug("TOP_MEM2: ");
|
||||||
|
print_debug_hex32(msr.hi);
|
||||||
|
print_debug_hex32(msr.lo);
|
||||||
|
print_debug("\r\n");
|
||||||
#endif
|
#endif
|
||||||
/* Check all of memory */
|
|
||||||
|
#if 0
|
||||||
|
ram_check(0x00000000, msr.lo+(msr.hi<<32));
|
||||||
|
#endif
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
msr_t msr;
|
// Check 16MB of memory @ 0
|
||||||
msr = rdmsr(TOP_MEM2);
|
ram_check(0x00000000, 0x00100000);
|
||||||
print_debug("TOP_MEM2: ");
|
// Check 16MB of memory @ 2GB
|
||||||
print_debug_hex32(msr.hi);
|
ram_check(0x80000000, 0x80100000);
|
||||||
print_debug_hex32(msr.lo);
|
|
||||||
print_debug("\r\n");
|
|
||||||
|
|
||||||
ram_check(0x00000000, msr.lo+(msr.hi<<32));
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
|
|
||||||
//#if TOTAL_CPUS < 2
|
|
||||||
// Check 16MB of memory @ 0
|
|
||||||
ram_check(0x00000000, 0x00100000);
|
|
||||||
//#else
|
|
||||||
// Check 16MB of memory @ 2GB
|
|
||||||
// ram_check(0x80000000, 0x80100000);
|
|
||||||
//#endif
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -10,26 +10,37 @@
|
||||||
const struct irq_routing_table intel_irq_routing_table = {
|
const struct irq_routing_table intel_irq_routing_table = {
|
||||||
PIRQ_SIGNATURE, /* u32 signature */
|
PIRQ_SIGNATURE, /* u32 signature */
|
||||||
PIRQ_VERSION, /* u16 version */
|
PIRQ_VERSION, /* u16 version */
|
||||||
32+16*11, /* there can be total 11 devices on the bus */
|
32+16*22, /* there can be total 22 devices on the bus */
|
||||||
3, /* Where the interrupt router lies (bus) */
|
1, /* Where the interrupt router lies (bus) */
|
||||||
(4<<3)|3, /* Where the interrupt router lies (dev) */
|
(4<<3)|3, /* Where the interrupt router lies (dev) */
|
||||||
0, /* IRQs devoted exclusively to PCI usage */
|
0, /* IRQs devoted exclusively to PCI usage */
|
||||||
0x1022, /* Vendor */
|
0x1022, /* Vendor */
|
||||||
0x746b, /* Device */
|
0x7400, /* Device */
|
||||||
0, /* Crap (miniport) */
|
0, /* Crap (miniport) */
|
||||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||||
0xd8, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
0x5b, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||||
{
|
{
|
||||||
{3,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
{0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
{0x6,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
|
{1,(3<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
{0x1,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0},
|
{0x4,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||||
{0x5,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
{0x4,0x8, {{0x1, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
{0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
{0x4,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||||
{0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
{0x4,0x18, {{0x2, 0xdef8}, {0x1, 0xdef8}, {0x3, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
{0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
{0x4,0x28, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
{0x6,(0x0a<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
{0x4,0x30, {{0x3, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
{0x4,(9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
{1,(4<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
{0x6,(0x0b<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
{1,(1<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
{0x2,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x2, 0},
|
||||||
|
{0x2,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x3, 0},
|
||||||
|
{0x2,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0x2,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{1,(2<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0x3,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x4, 0},
|
||||||
|
{0x3,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0},
|
||||||
|
{0x3,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
|
||||||
|
{0x3,0x28, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
|
||||||
|
{0,0xc8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0,0xd0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0,0xd8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -163,7 +163,7 @@ chip northbridge/amd/amdk8/root_complex
|
||||||
io 0x60 = 0x3f8
|
io 0x60 = 0x3f8
|
||||||
irq 0x70 = 4
|
irq 0x70 = 4
|
||||||
end
|
end
|
||||||
device pnp 2e.3 off # Com2
|
device pnp 2e.3 on # Com2
|
||||||
io 0x60 = 0x2f8
|
io 0x60 = 0x2f8
|
||||||
irq 0x70 = 3
|
irq 0x70 = 3
|
||||||
end
|
end
|
||||||
|
|
@ -177,8 +177,8 @@ chip northbridge/amd/amdk8/root_complex
|
||||||
io 0x60 = 0x100
|
io 0x60 = 0x100
|
||||||
end
|
end
|
||||||
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||||
io 0x60 = 0x201
|
io 0x60 = 0x220
|
||||||
io 0x62 = 0x330
|
io 0x62 = 0x300
|
||||||
irq 0x70 = 9
|
irq 0x70 = 9
|
||||||
end
|
end
|
||||||
device pnp 2e.8 off end # GPIO2
|
device pnp 2e.8 off end # GPIO2
|
||||||
|
|
@ -192,7 +192,101 @@ chip northbridge/amd/amdk8/root_complex
|
||||||
end
|
end
|
||||||
device pci 1.1 on end
|
device pci 1.1 on end
|
||||||
device pci 1.2 on end
|
device pci 1.2 on end
|
||||||
device pci 1.3 on end
|
device pci 1.3 on
|
||||||
|
chip drivers/i2c/i2cmux # pca9556 smbus mux
|
||||||
|
device i2c 18 on #0 pca9516 2, 1
|
||||||
|
chip drivers/i2c/lm63 #cpu0 temp
|
||||||
|
device i2c 4c on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device i2c 18 on #1 pca9516 1, 1
|
||||||
|
chip drivers/generic/generic #dimm 0-0-0
|
||||||
|
device i2c 50 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 0-0-1
|
||||||
|
device i2c 51 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 0-1-0
|
||||||
|
device i2c 52 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 0-1-1
|
||||||
|
device i2c 53 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device i2c 18 on #2 pca9516 1, 2
|
||||||
|
chip drivers/generic/generic #dimm 1-0-0
|
||||||
|
device i2c 50 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 1-0-1
|
||||||
|
device i2c 51 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 1-1-0
|
||||||
|
device i2c 52 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 1-1-1
|
||||||
|
device i2c 53 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device i2c 18 on #3 pca9516 1, 3
|
||||||
|
chip drivers/generic/generic #dimm 2-0-0
|
||||||
|
device i2c 50 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 2-0-1
|
||||||
|
device i2c 51 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 2-1-0
|
||||||
|
device i2c 52 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 2-1-1
|
||||||
|
device i2c 53 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device i2c 18 on #4 pca9516 1, 4
|
||||||
|
chip drivers/generic/generic #dimm 3-0-0
|
||||||
|
device i2c 50 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 3-0-1
|
||||||
|
device i2c 51 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 3-1-0
|
||||||
|
device i2c 52 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic #dimm 3-1-1
|
||||||
|
device i2c 53 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device i2c 18 on #5 pca9516 2, 2
|
||||||
|
chip drivers/i2c/lm63 #cpu1 temp
|
||||||
|
device i2c 4c on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device i2c 18 on #6 pca9516 2, 3
|
||||||
|
chip drivers/i2c/lm63 #cpu2 temp
|
||||||
|
device i2c 4c on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device i2c 18 on #7 pca9516 2, 4
|
||||||
|
chip drivers/i2c/lm63 #cpu3 temp
|
||||||
|
device i2c 4c on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end # i2cmux
|
||||||
|
chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN...
|
||||||
|
device i2c 2e on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid
|
||||||
|
device i2c 2a on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic # Winbond HWM 0x92
|
||||||
|
device i2c 49 on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic # Winbond HWM 0x94
|
||||||
|
device i2c 4a on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/generic # ??
|
||||||
|
device i2c 69 on end
|
||||||
|
end
|
||||||
|
end # acpi
|
||||||
device pci 1.5 off end
|
device pci 1.5 off end
|
||||||
device pci 1.6 off end
|
device pci 1.6 off end
|
||||||
end
|
end
|
||||||
|
|
@ -246,5 +340,12 @@ chip northbridge/amd/amdk8/root_complex
|
||||||
device apic 3 on end
|
device apic 3 on end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
chip drivers/generic/debug
|
||||||
|
device pnp 0.0 off end
|
||||||
|
device pnp 0.1 off end
|
||||||
|
device pnp 0.2 off end
|
||||||
|
device pnp 0.3 off end
|
||||||
|
device pnp 0.4 on end
|
||||||
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -2,7 +2,7 @@
|
||||||
* generic K8 debug code, used by mainboard specific auto.c
|
* generic K8 debug code, used by mainboard specific auto.c
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
#if 1
|
||||||
static void print_debug_pci_dev(unsigned dev)
|
static void print_debug_pci_dev(unsigned dev)
|
||||||
{
|
{
|
||||||
print_debug("PCI: ");
|
print_debug("PCI: ");
|
||||||
|
|
@ -17,7 +17,7 @@ static void print_pci_devices(void)
|
||||||
{
|
{
|
||||||
device_t dev;
|
device_t dev;
|
||||||
for(dev = PCI_DEV(0, 0, 0);
|
for(dev = PCI_DEV(0, 0, 0);
|
||||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
dev <= PCI_DEV(0xff, 0x1f, 0x7);
|
||||||
dev += PCI_DEV(0,0,1)) {
|
dev += PCI_DEV(0,0,1)) {
|
||||||
uint32_t id;
|
uint32_t id;
|
||||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||||
|
|
@ -56,7 +56,7 @@ static void dump_pci_devices(void)
|
||||||
{
|
{
|
||||||
device_t dev;
|
device_t dev;
|
||||||
for(dev = PCI_DEV(0, 0, 0);
|
for(dev = PCI_DEV(0, 0, 0);
|
||||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
dev <= PCI_DEV(0xff, 0x1f, 0x7);
|
||||||
dev += PCI_DEV(0,0,1)) {
|
dev += PCI_DEV(0,0,1)) {
|
||||||
uint32_t id;
|
uint32_t id;
|
||||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||||
|
|
@ -149,7 +149,9 @@ static void dump_smbus_registers(void)
|
||||||
}
|
}
|
||||||
status = smbus_read_byte(device, j);
|
status = smbus_read_byte(device, j);
|
||||||
if (status < 0) {
|
if (status < 0) {
|
||||||
print_debug("bad device\r\n");
|
print_debug("bad device status=");
|
||||||
|
print_debug_hex32(status);
|
||||||
|
print_debug("\r\n");
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
byte = status & 0xff;
|
byte = status & 0xff;
|
||||||
|
|
@ -159,3 +161,27 @@ static void dump_smbus_registers(void)
|
||||||
print_debug("\r\n");
|
print_debug("\r\n");
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void dump_io_resources(unsigned port)
|
||||||
|
{
|
||||||
|
|
||||||
|
int i;
|
||||||
|
udelay(2000);
|
||||||
|
print_debug_hex16(port);
|
||||||
|
print_debug(":\r\n");
|
||||||
|
for(i=0;i<256;i++) {
|
||||||
|
uint8_t val;
|
||||||
|
if ((i & 0x0f) == 0) {
|
||||||
|
print_debug_hex8(i);
|
||||||
|
print_debug_char(':');
|
||||||
|
}
|
||||||
|
val = inb(port);
|
||||||
|
print_debug_char(' ');
|
||||||
|
print_debug_hex8(val);
|
||||||
|
if ((i & 0x0f) == 0x0f) {
|
||||||
|
print_debug("\r\n");
|
||||||
|
}
|
||||||
|
port++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -27,7 +27,7 @@ static int lsmbus_recv_byte(device_t dev)
|
||||||
struct resource *res;
|
struct resource *res;
|
||||||
|
|
||||||
device = dev->path.u.i2c.device;
|
device = dev->path.u.i2c.device;
|
||||||
res = find_resource(dev->bus->dev, 0x20);
|
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
|
||||||
|
|
||||||
return do_smbus_recv_byte(res->base, device);
|
return do_smbus_recv_byte(res->base, device);
|
||||||
}
|
}
|
||||||
|
|
@ -38,7 +38,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val)
|
||||||
struct resource *res;
|
struct resource *res;
|
||||||
|
|
||||||
device = dev->path.u.i2c.device;
|
device = dev->path.u.i2c.device;
|
||||||
res = find_resource(dev->bus->dev, 0x20);
|
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
|
||||||
|
|
||||||
return do_smbus_send_byte(res->base, device, val);
|
return do_smbus_send_byte(res->base, device, val);
|
||||||
}
|
}
|
||||||
|
|
@ -50,7 +50,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
|
||||||
struct resource *res;
|
struct resource *res;
|
||||||
|
|
||||||
device = dev->path.u.i2c.device;
|
device = dev->path.u.i2c.device;
|
||||||
res = find_resource(dev->bus->dev, 0x20);
|
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
|
||||||
|
|
||||||
return do_smbus_read_byte(res->base, device, address);
|
return do_smbus_read_byte(res->base, device, address);
|
||||||
}
|
}
|
||||||
|
|
@ -61,7 +61,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
|
||||||
struct resource *res;
|
struct resource *res;
|
||||||
|
|
||||||
device = dev->path.u.i2c.device;
|
device = dev->path.u.i2c.device;
|
||||||
res = find_resource(dev->bus->dev, 0x20);
|
res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
|
||||||
|
|
||||||
return do_smbus_write_byte(res->base, device, address, val);
|
return do_smbus_write_byte(res->base, device, address, val);
|
||||||
}
|
}
|
||||||
|
|
@ -166,6 +166,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
|
||||||
.read_byte = lsmbus_read_byte,
|
.read_byte = lsmbus_read_byte,
|
||||||
.write_byte = lsmbus_write_byte,
|
.write_byte = lsmbus_write_byte,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct pci_operations lops_pci = {
|
static struct pci_operations lops_pci = {
|
||||||
.set_subsystem = lpci_set_subsystem,
|
.set_subsystem = lpci_set_subsystem,
|
||||||
};
|
};
|
||||||
|
|
@ -176,7 +177,7 @@ static struct device_operations acpi_ops = {
|
||||||
.enable_resources = acpi_enable_resources,
|
.enable_resources = acpi_enable_resources,
|
||||||
.init = acpi_init,
|
.init = acpi_init,
|
||||||
.scan_bus = scan_static_bus,
|
.scan_bus = scan_static_bus,
|
||||||
.enable = amd8111_enable,
|
// .enable = amd8111_enable,
|
||||||
.ops_pci = &lops_pci,
|
.ops_pci = &lops_pci,
|
||||||
.ops_smbus_bus = &lops_smbus_bus,
|
.ops_smbus_bus = &lops_smbus_bus,
|
||||||
};
|
};
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue