mb/google/dedede/var/metaknight: Update DPTF parameters
Remove TSR2 and use DPTF parameters from internal thermal team. BUG=b:175938681 TEST=build and boot to OS. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If0ec1ec48b8971efe87f1f8d10332a9c16352122 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raymond Wong <wongraymond@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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@ -64,7 +64,47 @@ chip soc/intel/jasperlake
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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}"
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register "power_limits_config" = "{
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.tdp_pl1_override = 6,
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.tdp_pl2_override = 12,
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}"
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device domain 0 on
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device pci 04.0 on
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chip drivers/intel/dptf
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register "options.tsr[0].desc" = ""Memory""
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register "options.tsr[1].desc" = ""CPU""
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 6000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000)}"
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)}"
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register "controls.power_limits.pl1" = "{
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.min_power = 3000,
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.max_power = 6000,
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.time_window_min = 1 * MSECS_PER_SEC,
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.time_window_max = 1 * MSECS_PER_SEC,
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.granularity = 125,}"
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register "controls.power_limits.pl2" = "{
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.min_power = 12000,
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.max_power = 12000,
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.time_window_min = 1 * MSECS_PER_SEC,
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.time_window_max = 1 * MSECS_PER_SEC,
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.granularity = 1000,}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf[0]" = "{ 255, 3000 }"
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register "controls.charger_perf[1]" = "{ 24, 1500 }"
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register "controls.charger_perf[2]" = "{ 16, 1000 }"
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register "controls.charger_perf[3]" = "{ 8, 500 }"
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device generic 0 on end
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end
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end # SA Thermal device
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device pci 14.0 on
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chip drivers/usb/acpi
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device usb 0.0 on
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