diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index e27aa685be..62f8b212e5 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -132,6 +132,24 @@ void soc_memory_init_params(struct romstage_params *params,
 		printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n");
 		reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events);
 	}
+
+	/* Update the UPD data for MemoryInit */
+	printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd);
+	upd->PcdSerialRegisterBase = UART_BASE_ADDRESS;
+	upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
+		config->PcdSmmTsegSize : 0;
+}
+
+void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
+	MEMORY_INIT_UPD *new)
+{
+	/* Display the parameters for MemoryInit */
+	printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new);
+	fsp_display_upd_value("PcdSerialRegisterBase",
+		sizeof(old->PcdSerialRegisterBase),
+		old->PcdSerialRegisterBase, new->PcdSerialRegisterBase);
+	fsp_display_upd_value("PcdSmmTsegSize", sizeof(old->PcdSmmTsegSize),
+		old->PcdSmmTsegSize, new->PcdSmmTsegSize);
 }
 
 void soc_after_ram_init(struct romstage_params *params)
@@ -157,8 +175,3 @@ void soc_after_ram_init(struct romstage_params *params)
 	/* Initialize the PCIe bridges */
 	pcie_init();
 }
-
-void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
-	MEMORY_INIT_UPD *new)
-{
-}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
index ef0cf092e5..86f548777c 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
+++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
@@ -77,39 +77,39 @@ typedef struct {
 
 
 typedef struct {
-/** Offset 0x0020
+/** Offset 0x0018
 **/
   UINT64                      Signature;
-/** Offset 0x0028
+/** Offset 0x0020
 **/
   UINT64                      Revision;
-/** Offset 0x0030
+/** Offset 0x0028
 **/
   UINT32                      PcdRmuBinaryBaseAddress;
+/** Offset 0x002C
+**/
+  UINT32                      UnusedUpdSpace0;
+/** Offset 0x0030
+**/
+  UINT32                      PcdSerialRegisterBase;
 /** Offset 0x0034
-**/
-  UINT32                      PcdRmuBinaryLen;
-/** Offset 0x0038
 **/
   UINT8                       PcdSmmTsegSize;
-/** Offset 0x0039
+/** Offset 0x0035
 **/
-  UINT8                       PcdPlatformType;
-/** Offset 0x003A
-**/
-  UINT8                       ReservedMemoryInitUpd[22];
+  UINT8                       ReservedMemoryInitUpd[3];
 } MEMORY_INIT_UPD;
 
 typedef struct {
-/** Offset 0x0050
+/** Offset 0x0038
 **/
   UINT64                      Signature;
-/** Offset 0x0058
+/** Offset 0x0040
 **/
   UINT64                      Revision;
-/** Offset 0x0060
+/** Offset 0x0048
 **/
-  UINT8                       ReservedSiliconInitUpd[32];
+  UINT16                      PcdRegionTerminator;
 } SILICON_INIT_UPD;
 
 #define FSP_UPD_SIGNATURE                0x244450554B525124        /* '$QRKUPD$' */
@@ -130,17 +130,11 @@ typedef struct _UPD_DATA_REGION {
 **/
   UINT32                      SiliconInitUpdOffset;
 /** Offset 0x0018
-**/
-  UINT64                      ReservedUpd1;
-/** Offset 0x0020
 **/
   MEMORY_INIT_UPD             MemoryInitUpd;
-/** Offset 0x0050
+/** Offset 0x0038
 **/
   SILICON_INIT_UPD            SiliconInitUpd;
-/** Offset 0x0080
-**/
-  UINT16                      PcdRegionTerminator;
 } UPD_DATA_REGION;
 
 #define FSP_IMAGE_ID    0x305053462D4B5551        /* 'QUK-FSP0' */