diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c
index 322d241164..9549537261 100644
--- a/src/soc/imgtec/pistachio/ddr2_init.c
+++ b/src/soc/imgtec/pistachio/ddr2_init.c
@@ -112,7 +112,7 @@ int init_ddr2(void)
 	 * 15:13 RSVD RSVD
 	 * 31:16 Reserved
 	 */
-	write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000A62 | (BL8 ? 0x1 : 0x0));
+	write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00000B62 | (BL8 ? 0x1 : 0x0));
 	/* MR1 : EMR Register
 	 * Generate to use with PHY and PCTL
 	 * 0 DE DLL Enable 0 Disable 1
diff --git a/src/soc/imgtec/pistachio/ddr3_init.c b/src/soc/imgtec/pistachio/ddr3_init.c
index e77a5cde9c..5cb36a07b8 100644
--- a/src/soc/imgtec/pistachio/ddr3_init.c
+++ b/src/soc/imgtec/pistachio/ddr3_init.c
@@ -119,7 +119,7 @@ int init_ddr3(void)
 	 * 15:13 RSVD RSVD
 	 * 31:16 Reserved
 	 */
-	write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001420);
+	write32(DDR_PHY + DDRPHY_MR_OFFSET, 0x00001520);
 	/* MR1 : DDR3 mode register 1
 	 * Generate to use with PHY and PCTL
 	 * 0 DE DLL Enable 0 Disable 1