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soc/intel/tigerlake: Add ACPI addition for USB4/TBT latency optimization 

The PCI-SIG engineering change requirement provides the ACPI additions
for firmware latency optimization. This change adds additional ACPI DSM
function with both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME to the
USB4/TBT topology. The OS is informed to reduce latency for upstream
ports while connecting USB4/TBT devices.

BUG=b:199757442
TEST=It was validated that the first connected device waits only 50ms
instead of 100ms and all functions work on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I5a19118b75ed0a78b7436f2f90295c03928300d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
John Zhao 2021-09-13 12:31:39 -07:00 committed by Felix Held
parent e0bff814da
commit 7227cef0d7
1 changed files with 59 additions and 0 deletions
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59
src/soc/intel/tigerlake/acpi/tcss_pcierp.asl
View File

@ -1,5 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency
* optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream
* port of the USB4/TBT topology.
*/
/* Number of microseconds to wait after a conventional reset */
#define FW_RESET_TIME 50000
/* Number of microseconds to wait after data link layer active report */
#define FW_DL_UP_TIME 1
/* Number of microseconds to wait after a function level reset */
#define FW_FLR_RESET_TIME 1
/* Number of microseconds to wait from D3 hot to D0 transition */
#define FW_D3HOT_TO_D0_TIME 50000
/* Number of microseconds to wait after setting the VF enable bit */
#define FW_VF_ENABLE_TIME 1
OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800) OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800)
Field (PXCS, AnyAcc, NoLock, Preserve) Field (PXCS, AnyAcc, NoLock, Preserve)
{ {
@ -64,10 +84,49 @@ Method (_DSM, 4, Serialized)
Return (Buffer() { 0x00 }) Return (Buffer() { 0x00 })
} }
/*
* A bitmask of functions support
*/
Name(OPTS, Buffer(2) {0, 0})
Device (PXSX) Device (PXSX)
{ {
Name (_ADR, 0x00000000) Name (_ADR, 0x00000000)
/*
* _DSM Device Specific Method
*
* Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D
* Arg1: Revision ID: 3
* Arg2: Function index: 0, 9
* Arg3: Empty package
*/
Method (_DSM, 4, Serialized)
{
If (Arg0 == ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D")) {
If (Arg1 >= 3) {
If (Arg2 == 0) {
/*
* Function index: 0
* Standard query - A bitmask of functions supported
*/
CreateBitField(OPTS, 9, FUN9)
FUN9 = 1
Return (OPTS)
} ElseIf (Arg2 == 9) {
/*
* Function index: 9
* Specifying device readiness durations
*/
Return (Package() { FW_RESET_TIME, FW_DL_UP_TIME,
FW_FLR_RESET_TIME, FW_D3HOT_TO_D0_TIME,
FW_VF_ENABLE_TIME })
}
}
}
Return (Buffer() { 0x0 })
}
Method (_PRW, 0) Method (_PRW, 0)
{ {
Return (Package() { 0x69, 4 }) Return (Package() { 0x69, 4 })