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soc/intel/skylake: Use intel common support to write-protect SPI flash 

BUG=chrome-os-partner:58896

Change-Id: I281c799a1798f3353d78edd8a6cd16bbe762bc2c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17116
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Furquan Shaikh 2016-10-24 15:27:21 -07:00 committed by Furquan Shaikh
parent aedbfc8f09
commit 723a84e292
3 changed files with 6 additions and 38 deletions
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1
src/soc/intel/skylake/Kconfig
View File

@ -44,6 +44,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_SPI_PROTECT
select SMM_TSEG
select SMP
select SSE2

31
src/soc/intel/skylake/flash_controller.c
View File

@ -21,6 +21,7 @@
#include <spi_flash.h>
#include <timer.h>
#include <soc/flash_controller.h>
#include <soc/intel/common/spi.h>
#include <soc/pci_devs.h>
#include <soc/spi.h>
@ -386,40 +387,16 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
return slave;
}
int spi_flash_protect(u32 start, u32 size)
int spi_get_fpr_info(struct fpr_info *info)
{
pch_spi_regs *spi_bar = get_spi_bar();
u32 end = start + size - 1;
u32 reg;
int prr;
if (!spi_bar)
return -1;
/* Find first empty PRR */
for (prr = 0; prr < SPI_PRR_MAX; prr++) {
reg = read32(&spi_bar->pr[prr]);
if (reg == 0)
break;
}
if (prr >= SPI_PRR_MAX) {
printk(BIOS_ERR, "ERROR: No SPI PRR free!\n");
return -1;
}
info->base = (uintptr_t)&spi_bar->pr[0];
info->max = SPI_FPR_MAX;
/* Set protected range base and limit */
reg = SPI_PRR(start, end) | SPI_PRR_WPE;
/* Set the PRR register and verify it is protected */
write32(&spi_bar->pr[prr], reg);
reg = read32(&spi_bar->pr[prr]);
if (!(reg & SPI_PRR_WPE)) {
printk(BIOS_ERR, "ERROR: Unable to set SPI PRR %d\n", prr);
return -1;
}
printk(BIOS_INFO, "%s: PRR %d is enabled for range 0x%08x-0x%08x\n",
__func__, prr, start, end);
return 0;
}

12
src/soc/intel/skylake/include/soc/spi.h
View File

@ -40,16 +40,7 @@
/* STRAP Data Register*/
#define SPIBAR_RESET_DATA 0xF8
#define SPI_PRR_MAX 5
#define SPI_PRR_SHIFT 12
#define SPI_PRR_MASK 0x7fff
#define SPI_PRR_BASE_SHIFT 0
#define SPI_PRR_LIMIT_SHIFT 16
#define SPI_PRR_RPE (1 << 15) /* Read Protect */
#define SPI_PRR_WPE (1 << 31) /* Write Protect */
#define SPI_PRR(base, limit) \
(((((limit) >> SPI_PRR_SHIFT) & SPI_PRR_MASK) << SPI_PRR_LIMIT_SHIFT) |\
((((base) >> SPI_PRR_SHIFT) & SPI_PRR_MASK) << SPI_PRR_BASE_SHIFT))
#define SPI_FPR_MAX 5
#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
#define SPI_OPTYPE_0 0x01 /* Write, no address */
@ -131,6 +122,5 @@
#define SPIBAR_BC_WPD (1 << 0)
void *get_spi_bar(void);
int spi_flash_protect(u32 start, u32 size);
#endif