soc/intel/skylake: Use intel common support to write-protect SPI flash
BUG=chrome-os-partner:58896 Change-Id: I281c799a1798f3353d78edd8a6cd16bbe762bc2c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17116 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -44,6 +44,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_LPSS_I2C
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select SOC_INTEL_COMMON_NHLT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_SPI_PROTECT
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select SMM_TSEG
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select SMP
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select SSE2
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@ -21,6 +21,7 @@
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#include <spi_flash.h>
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#include <timer.h>
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#include <soc/flash_controller.h>
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#include <soc/intel/common/spi.h>
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#include <soc/pci_devs.h>
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#include <soc/spi.h>
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@ -386,40 +387,16 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
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return slave;
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}
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int spi_flash_protect(u32 start, u32 size)
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int spi_get_fpr_info(struct fpr_info *info)
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{
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pch_spi_regs *spi_bar = get_spi_bar();
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u32 end = start + size - 1;
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u32 reg;
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int prr;
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if (!spi_bar)
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return -1;
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/* Find first empty PRR */
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for (prr = 0; prr < SPI_PRR_MAX; prr++) {
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reg = read32(&spi_bar->pr[prr]);
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if (reg == 0)
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break;
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}
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if (prr >= SPI_PRR_MAX) {
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printk(BIOS_ERR, "ERROR: No SPI PRR free!\n");
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return -1;
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}
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info->base = (uintptr_t)&spi_bar->pr[0];
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info->max = SPI_FPR_MAX;
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/* Set protected range base and limit */
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reg = SPI_PRR(start, end) | SPI_PRR_WPE;
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/* Set the PRR register and verify it is protected */
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write32(&spi_bar->pr[prr], reg);
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reg = read32(&spi_bar->pr[prr]);
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if (!(reg & SPI_PRR_WPE)) {
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printk(BIOS_ERR, "ERROR: Unable to set SPI PRR %d\n", prr);
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return -1;
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}
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printk(BIOS_INFO, "%s: PRR %d is enabled for range 0x%08x-0x%08x\n",
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__func__, prr, start, end);
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return 0;
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}
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@ -40,16 +40,7 @@
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/* STRAP Data Register*/
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#define SPIBAR_RESET_DATA 0xF8
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#define SPI_PRR_MAX 5
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#define SPI_PRR_SHIFT 12
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#define SPI_PRR_MASK 0x7fff
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#define SPI_PRR_BASE_SHIFT 0
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#define SPI_PRR_LIMIT_SHIFT 16
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#define SPI_PRR_RPE (1 << 15) /* Read Protect */
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#define SPI_PRR_WPE (1 << 31) /* Write Protect */
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#define SPI_PRR(base, limit) \
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(((((limit) >> SPI_PRR_SHIFT) & SPI_PRR_MASK) << SPI_PRR_LIMIT_SHIFT) |\
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((((base) >> SPI_PRR_SHIFT) & SPI_PRR_MASK) << SPI_PRR_BASE_SHIFT))
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#define SPI_FPR_MAX 5
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#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
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#define SPI_OPTYPE_0 0x01 /* Write, no address */
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@ -131,6 +122,5 @@
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#define SPIBAR_BC_WPD (1 << 0)
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void *get_spi_bar(void);
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int spi_flash_protect(u32 start, u32 size);
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#endif
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