GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

inteltool: add 300 and C240 Series PCH 

Values from
- Intel doc 337347 rev4
- coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h

On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not
accessible. Using a static value instead. 0xfd000000 is a common value
chosen by coreboot and non-coreboot firmware.

Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Thomas Heijligen 2019-02-19 10:51:34 +00:00 committed by Patrick Georgi
parent 02bd77379b
commit 725369fd0c
5 changed files with 626 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
util/inteltool/gpio.c
View File

@ -1034,6 +1034,16 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
case PCI_DEVICE_ID_INTEL_H310:
case PCI_DEVICE_ID_INTEL_H370:
case PCI_DEVICE_ID_INTEL_Z390:
case PCI_DEVICE_ID_INTEL_Q370:
case PCI_DEVICE_ID_INTEL_B360:
case PCI_DEVICE_ID_INTEL_C246:
case PCI_DEVICE_ID_INTEL_C242:
case PCI_DEVICE_ID_INTEL_QM370:
case PCI_DEVICE_ID_INTEL_HM370:
case PCI_DEVICE_ID_INTEL_CM246:
print_gpio_groups(sb); print_gpio_groups(sb);
return 0; return 0;
case PCI_DEVICE_ID_INTEL_82371XX: case PCI_DEVICE_ID_INTEL_82371XX:

552
util/inteltool/gpio_groups.c
View File

@ -1181,6 +1181,527 @@ static const struct gpio_community *const denverton_communities[] = {
&denverton_community_north, &denverton_community_south, &denverton_community_north, &denverton_community_south,
}; };
static const char *const cannonlake_pch_h_group_a_names[] = {
"GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#",
"GPP_A1", "LAD0", "n/a", "ESPI_IO0",
"GPP_A2", "LAD1", "n/a", "ESPI_IO1",
"GPP_A3", "LAD2", "n/a", "ESPI_IO2",
"GPP_A4", "LAD3", "n/a", "ESPI_IO3",
"GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#",
"GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#",
"GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#",
"GPP_A8", "CLKRUN#", "n/a", "n/a",
"GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
"GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
"GPP_A11", "PME#", "SD_VDD2_PWR_EN#", "n/a",
"GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
"GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
"GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
"GPP_A15", "SUSACK#", "n/a", "n/a",
"GPP_A16", "CLKOUT_48", "n/a", "n/a",
"GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a",
"GPP_A18", "ISH_GP0", "n/a", "n/a",
"GPP_A19", "ISH_GP1", "n/a", "n/a",
"GPP_A20", "ISH_GP2", "n/a", "n/a",
"GPP_A21", "ISH_GP3", "n/a", "n/a",
"GPP_A22", "ISH_GP4", "n/a", "n/a",
"GPP_A23", "ISH_GP5", "n/a", "n/a",
"GPIO_RSVD_0", "n/a", "n/a", "n/a",
};
static const struct gpio_group cannonlake_pch_h_group_a = {
.display = "------- GPIO Group GPP_A -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_a_names) / 4,
.func_count = 4,
.pad_names = cannonlake_pch_h_group_a_names,
};
static const char *const cannonlake_pch_h_group_b_names[] = {
"GPP_B0", "GSPI0_CS1#", "n/a",
"GPP_B1", "GSPI1_CS1#", "TIME_SYNC1",
"GPP_B2", "VRALERT#", "n/a",
"GPP_B3", "CPU_GP2", "n/a",
"GPP_B4", "CPU_GP3", "n/a",
"GPP_B5", "SRCCLKREQ0#", "n/a",
"GPP_B6", "SRCCLKREQ1#", "n/a",
"GPP_B7", "SRCCLKREQ2#", "n/a",
"GPP_B8", "SRCCLKREQ3#", "n/a",
"GPP_B9", "SRCCLKREQ4#", "n/a",
"GPP_B10", "SRCCLKREQ5#", "n/a",
"GPP_B11", "I2S_MCLK", "n/a",
"GPP_B12", "SLP_S0#", "n/a",
"GPP_B13", "PLTRST#", "n/a",
"GPP_B14", "SPKR", "n/a",
"GPP_B15", "GSPI0_CS0#", "n/a",
"GPP_B16", "GSPI0_CLK", "n/a",
"GPP_B17", "GSPI0_MISO", "n/a",
"GPP_B18", "GSPI0_MOSI", "n/a",
"GPP_B19", "GSPI1_CS0#", "n/a",
"GPP_B20", "GSPI1_CLK", "n/a",
"GPP_B21", "GSPI1_MISO", "n/a",
"GPP_B22", "GSPI1_MOSI", "n/a",
"GPP_B23", "SML1ALERT#", "PCHHOT#",
"GPIO_RSVD_1", "n/a", "n/a",
"GPIO_RSVD_2", "n/a", "n/a",
};
static const struct gpio_group cannonlake_pch_h_group_b = {
.display = "------- GPIO Group GPP_B -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_b_names) / 3,
.func_count = 3,
.pad_names = cannonlake_pch_h_group_b_names,
};
static const char *const cannonlake_pch_h_group_c_names[] = {
"GPP_C0", "SMBCLK", "n/a",
"GPP_C1", "SMBDATA", "n/a",
"GPP_C2", "SMBALERT#", "n/a",
"GPP_C3", "SML0CLK", "n/a",
"GPP_C4", "SML0DATA", "n/a",
"GPP_C5", "SML0ALERT#", "n/a",
"GPP_C6", "SML1CLK", "n/a",
"GPP_C7", "SML1DATA", "n/a",
"GPP_C8", "UART0A_RXD", "n/a",
"GPP_C9", "UART0A_TXD", "n/a",
"GPP_C10", "UART0A_RTS#", "n/a",
"GPP_C11", "UART0A_CTS#", "n/a",
"GPP_C12", "UART1_RXD", "ISH_UART1_RXD",
"GPP_C13", "UART1_TXD", "ISH_UART1_TXD",
"GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#",
"GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#",
"GPP_C16", "I2C0_SDA", "n/a",
"GPP_C17", "I2C0_SCL", "n/a",
"GPP_C18", "I2C1_SDA", "n/a",
"GPP_C19", "I2C1_SCL", "n/a",
"GPP_C20", "UART2_RXD", "n/a",
"GPP_C21", "UART2_TXD", "n/a",
"GPP_C22", "UART2_RTS#", "n/a",
"GPP_C23", "UART2_CTS#", "n/a",
};
static const struct gpio_group cannonlake_pch_h_group_c = {
.display = "------- GPIO Group GPP_C -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_c_names) / 3,
.func_count = 3,
.pad_names = cannonlake_pch_h_group_c_names,
};
static const char *const cannonlake_pch_h_group_d_names[] = {
"GPP_D0", "SPI1_CS#", "n/a", "SBK0", "BK0",
"GPP_D1", "SPI1_CLK", "n/a", "SBK1", "BK1",
"GPP_D2", "SPI1_MISO", "n/a", "SBK2", "BK2",
"GPP_D3", "SPI1_MOSI", "n/a", "SBK3", "BK3",
"GPP_D4", "I2C2_SDA", "I2C3_SDA", "SBK4", "BK4",
"GPP_D5", "I2S2_SFRM", "n/a", "CNV_RF_RESET#", "n/a",
"GPP_D6", "I2S2_TXD", "n/a", "MODEM_CLKREQ", "n/a",
"GPP_D7", "I2S2_RXD", "n/a", "n/a", "n/a",
"GPP_D8", "I2S2_SCLK", "n/a", "n/a", "n/a",
"GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", "n/a",
"GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", "n/a",
"GPP_D11", "ISH_SPI_MISO", "GP_BSSB_CLK", "GSPI2_MISO", "n/a",
"GPP_D12", "ISH_SPI_MOSI", "GP_BSSB_DI", "GSPI2_MOSI", "n/a",
"GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", "n/a",
"GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", "n/a",
"GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", "CNV_WFEN",
"GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", "CNV_WCEN",
"GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", "n/a",
"GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", "n/a",
"GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", "n/a",
"GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", "n/a",
"GPP_D21", "SPI1_IO2", "n/a", "n/a", "n/a",
"GPP_D22", "SPI1_IO3", "n/a", "n/a", "n/a",
"GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", "n/a",
};
static const struct gpio_group cannonlake_pch_h_group_d = {
.display = "------- GPIO Group GPP_D -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_d_names) / 5,
.func_count = 5,
.pad_names = cannonlake_pch_h_group_d_names,
};
static const char *const cannonlake_pch_h_group_e_names[] = {
"GPP_E0", "SATAXPCIE0", "SATAGP0",
"GPP_E1", "SATAXPCIE1", "SATAGP1",
"GPP_E2", "SATAXPCIE2", "SATAGP2",
"GPP_E3", "CPU_GP0", "n/a",
"GPP_E4", "SATA_DEVSLP0", "n/a",
"GPP_E5", "SATA_DEVSLP1", "n/a",
"GPP_E6", "SATA_DEVSLP2", "n/a",
"GPP_E7", "CPU_GP1", "n/a",
"GPP_E8", "SATALED#", "n/a",
"GPP_E9", "USB2_OC0#", "n/a",
"GPP_E10", "USB2_OC1#", "n/a",
"GPP_E11", "USB2_OC2#", "n/a",
"GPP_E12", "USB2_OC3#", "n/a",
};
static const struct gpio_group cannonlake_pch_h_group_e = {
.display = "------- GPIO Group GPP_E -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_e_names) / 3,
.func_count = 3,
.pad_names = cannonlake_pch_h_group_e_names,
};
static const char *const cannonlake_pch_h_group_f_names[] = {
"GPP_F0", "SATAXPCIE3", "SATAGP3",
"GPP_F1", "SATAXPCIE4", "SATAGP4",
"GPP_F2", "SATAXPCIE5", "SATAGP5",
"GPP_F3", "SATAXPCIE6", "SATAGP6",
"GPP_F4", "SATAXPCIE7", "SATAGP7",
"GPP_F5", "SATA_DEVSLP3", "n/a",
"GPP_F6", "SATA_DEVSLP4", "n/a",
"GPP_F7", "SATA_DEVSLP5", "n/a",
"GPP_F8", "SATA_DEVSLP6", "n/a",
"GPP_F9", "SATA_DEVSLP7", "n/a",
"GPP_F10", "SATA_SCLOCK", "n/a",
"GPP_F11", "SATA_SLOAD", "n/a",
"GPP_F12", "SATA_SDATAOUT1", "n/a",
"GPP_F13", "SATA_SDATAOUT0", "n/a",
"GPP_F14", "n/a", "PS_ON#",
"GPP_F15", "USB2_OC4#", "n/a",
"GPP_F16", "USB2_OC5#", "n/a",
"GPP_F17", "USB2_OC6#", "n/a",
"GPP_F18", "USB2_OC7#", "n/a",
"GPP_F19", "eDP_VDDEN", "n/a",
"GPP_F20", "eDP_BKLTEN", "n/a",
"GPP_F21", "eDP_BKLTCTL", "n/a",
"GPP_F22", "DDPF_CTRLCLK", "n/a",
"GPP_F23", "DDPF_CTRLDATA", "n/a",
};
static const struct gpio_group cannonlake_pch_h_group_f = {
.display = "------- GPIO Group GPP_F -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_f_names) / 3,
.func_count = 3,
.pad_names = cannonlake_pch_h_group_f_names,
};
static const char *const cannonlake_pch_h_group_spi_names[] = {
"GPIO_RSVD_11",
"GPIO_RSVD_12",
"GPIO_RSVD_13",
"GPIO_RSVD_14",
"GPIO_RSVD_15",
"GPIO_RSVD_16",
"GPIO_RSVD_17",
"GPIO_RSVD_18",
"GPIO_RSVD_19",
};
static const struct gpio_group cannonlake_pch_h_group_spi = {
.display = "------- GPIO Group SPI -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_spi_names) / 1,
.func_count = 1,
.pad_names = cannonlake_pch_h_group_spi_names,
};
static const char *const cannonlake_pch_h_group_g_names[] = {
"GPP_G0", "SD_CMD",
"GPP_G1", "SD_DATA0",
"GPP_G2", "SD_DATA1",
"GPP_G3", "SD_DATA2",
"GPP_G4", "SD_DATA3",
"GPP_G5", "SD_CD#",
"GPP_G6", "SD_CLK",
"GPP_G7", "SD_WP",
};
static const struct gpio_group cannonlake_pch_h_group_g = {
.display = "------- GPIO Group GPP_G -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_g_names) / 2,
.func_count = 2,
.pad_names = cannonlake_pch_h_group_g_names,
};
static const char *const cannonlake_pch_h_group_aza_names[] = {
"GPIO_RSVD_3",
"GPIO_RSVD_4",
"GPIO_RSVD_5",
"GPIO_RSVD_6",
"GPIO_RSVD_7",
"GPIO_RSVD_8",
"GPIO_RSVD_9",
"GPIO_RSVD_10",
};
static const struct gpio_group cannonlake_pch_h_group_aza = {
.display = "------- GPIO Grpoup AZA -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_aza_names) / 1,
.func_count = 1,
.pad_names = cannonlake_pch_h_group_aza_names,
};
static const char *const cannonlake_pch_h_group_vgpio_0_names[] = {
"CNV_BTEN",
"CNV_GNEN",
"CNV_WFEN",
"CNV_WCEN",
"CNV_BT_HOST_WAKEB",
"vCNV_GNSS_HOST_WAKEB",
"vSD3_CD_B",
"CNV_BT_IF_SELECT",
"vCNV_BT_UART_TXD",
"vCNV_BT_UART_RXD",
"vCNV_BT_UART_CTS_B",
"vCNV_BT_UART_RTS_B",
"vCNV_MFUART1_TXD",
"vCNV_MFUART1_RXD",
"vCNV_MFUART1_CTS_B",
"vCNV_MFUART1_RTS_B",
"vCNV_GNSS_UART_TXD",
"vCNV_GNSS_UART_RXD",
"vCNV_GNSS_UART_CTS_B",
"vCNV_GNSS_UART_RTS_B",
"vUART0_TXD",
"vUART0_RXD",
"vUART0_CTS_B",
"vUART0_RTSB",
"vISH_UART0_TXD",
"vISH_UART0_RXD",
"vISH_UART0_CTS_B",
"vISH_UART0_RTSB",
"vISH_UART1_TXD",
"vISH_UART1_RXD",
"vISH_UART1_CTS_B",
"vISH_UART1_RTS_B",
};
static const struct gpio_group cannonlake_pch_h_group_vgpio_0 = {
.display = "------- GPIO Grpoup VGPIO_0 -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_0_names) / 1,
.func_count = 1,
.pad_names = cannonlake_pch_h_group_vgpio_0_names,
};
static const char *const cannonlake_pch_h_group_vgpio_1_names[] = {
"vCNV_BT_I2S_BCLK",
"vCNV_BT_I2S_WS_SYNC",
"vCNV_BT_I2S_SDO",
"vCNV_BT_I2S_SDI",
"vSSP2_SCLK",
"vSSP2_SFRM",
"vSSP2_TXD",
"vSSP2_RXD",
};
static const struct gpio_group cannonlake_pch_h_group_vgpio_1 = {
.display = "------- GPIO Grpoup VGPIO_1 -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_1_names) / 1,
.func_count = 1,
.pad_names = cannonlake_pch_h_group_vgpio_1_names,
};
static const char *const cannonlake_pch_h_group_h_names[] = {
"GPP_H0", "SRCCLKREQ6#",
"GPP_H1", "SRCCLKREQ7#",
"GPP_H2", "SRCCLKREQ8#",
"GPP_H3", "SRCCLKREQ9#",
"GPP_H4", "SRCCLKREQ10#",
"GPP_H5", "SRCCLKREQ11#",
"GPP_H6", "SRCCLKREQ12#",
"GPP_H7", "SRCCLKREQ13#",
"GPP_H8", "SRCCLKREQ14#",
"GPP_H9", "SRCCLKREQ15#",
"GPP_H10", "SML2CLK",
"GPP_H11", "SML2DATA",
"GPP_H12", "SML2ALERT#",
"GPP_H13", "SML3CLK",
"GPP_H14", "SML3DATA",
"GPP_H15", "SML3ALERT#",
"GPP_H16", "SML4CLK",
"GPP_H17", "SML4DATA",
"GPP_H18", "SML4ALERT#",
"GPP_H19", "ISH_I2C0_SDA",
"GPP_H20", "ISH_I2C0_SCL",
"GPP_H21", "ISH_I2C1_SDA",
"GPP_H22", "ISH_I2C1_SCL",
"GPP_H23", "TIME_SYNC0",
};
static const struct gpio_group cannonlake_pch_h_group_h = {
.display = "------- GPIO Group GPP_H -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_h_names) / 2,
.func_count = 2,
.pad_names = cannonlake_pch_h_group_h_names,
};
static const char *const cannonlake_pch_h_group_i_names[] = {
"GPP_I0", "DDPB_HPD0", "DISP_MISC0",
"GPP_I1", "DDPB_HPD1", "DISP_MISC1",
"GPP_I2", "DDPB_HPD2", "DISP_MISC2",
"GPP_I3", "DDPB_HPD3", "DISP_MISC3",
"GPP_I4", "EDP_HPD", "DISP_MISC4",
"GPP_I5", "DDPB_CTRLCLK", "n/a",
"GPP_I6", "DDPB_CTRLDATA", "n/a",
"GPP_I7", "DDPC_CTRLCLK", "n/a",
"GPP_I8", "DDPC_CTRLDATA", "n/a",
"GPP_I9", "DDPD_CTRLCLK", "n/a",
"GPP_I10", "DDPD_CTRLDATA", "n/a",
"GPP_I11", "M2_SKT2_CFG0", "n/a",
"GPP_I12", "M2_SKT2_CFG1", "n/a",
"GPP_I13", "M2_SKT2_CFG2", "n/a",
"GPP_I14", "M2_SKT2_CFG3", "n/a",
"GPIO_RSVD_40", "n/a", "n/a",
"GPIO_RSVD_41", "n/a", "n/a",
"GPIO_RSVD_42", "n/a", "n/a",
};
static const struct gpio_group cannonlake_pch_h_group_i = {
.display = "-------GPIO Group GPP_I -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_i_names) / 3,
.func_count = 3,
.pad_names = cannonlake_pch_h_group_i_names,
};
static const char *const cannonlake_pch_h_group_j_names[] = {
"GPP_J0", "CNV_PA_BLANKING", "n/a",
"GPP_J1", "n/a", "CPU_C10_GATE#",
"GPP_J2", "n/a", "n/a",
"GPP_J3", "n/a", "n/a",
"GPP_J4", "CNV_BRI_DT", "UART0B_RTS#",
"GPP_J5", "CNV_BRI_RSP", "UART0B_RXD",
"GPP_J6", "CNV_RGI_DT", "UART0B_TXD",
"GPP_J7", "CNV_RGI_RSP", "UART0B_CTS#",
"GPP_J8", "CNV_MFUART2_RXD", "n/a",
"GPP_J9", "CNV_MFUART2_TXD", "n/a",
"GPP_J10", "n/a", "n/a",
"GPP_J11", "A4WP_PRESENT", "n/a",
};
static const struct gpio_group cannonlake_pch_h_group_j = {
.display = "------- GPIO Group GPP_J -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_j_names) / 3,
.func_count = 3,
.pad_names = cannonlake_pch_h_group_j_names,
};
static const char *const cannonlake_pch_h_group_k_names[] = {
"GPP_K0", "n/a",
"GPP_K1", "n/a",
"GPP_K2", "n/a",
"GPP_K3", "n/a",
"GPP_K4", "n/a",
"GPP_K5", "n/a",
"GPP_K6", "n/a",
"GPP_K7", "n/a",
"GPP_K8", "Reserved",
"GPP_K9", "Reserved",
"GPP_K10", "Reserved",
"GPP_K11", "Reserved",
"GPP_K12", "GSXOUT",
"GPP_K13", "GSXSLOAD",
"GPP_K14", "GSXDIN",
"GPP_K15", "GSXSRESET#",
"GPP_K16", "GSXCLK",
"GPP_K17", "ADR_COMPLETE",
"GPP_K18", "NMI#",
"GPP_K19", "SMI#",
"GPP_K20", "Reserved",
"GPP_K21", "Reserved",
"GPP_K22", "IMGCLKOUT0",
"GPP_K23", "IMGCLKOUT1",
};
static const struct gpio_group cannonlake_pch_h_group_k = {
.display = "------- GPIO Group GPP_K -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_k_names) / 2,
.func_count = 2,
.pad_names = cannonlake_pch_h_group_k_names,
};
static const char *const cannonlake_pch_h_group_gpd_names[] = {
"GPD0", "BATLOW#",
"GPD1", "ACPRESENT",
"GPD2", "LAN_WAKE#",
"GPD3", "PRWBTN#",
"GPD4", "SLP_S3#",
"GPD5", "SLP_S4#",
"GPD6", "SLP_A#",
"GPD7", "n/a",
"GPD8", "SUSCLK",
"GPD9", "SLP_WLAN#",
"GPD10", "SLP_S5#",
"GPD11", "LANPHYPC",
};
static const struct gpio_group cannonlake_pch_h_group_gpd = {
.display = "------- GPIO Group GPD -------",
.pad_count = ARRAY_SIZE(cannonlake_pch_h_group_gpd_names) / 2,
.func_count = 2,
.pad_names = cannonlake_pch_h_group_gpd_names,
};
static const struct gpio_group *const cannonlake_pch_h_community_0_groups[] = {
&cannonlake_pch_h_group_a,
&cannonlake_pch_h_group_b,
};
static const struct gpio_community cannonlake_pch_h_community_0 = {
.name = "------- GPIO Community 0 -------",
.pcr_port_id = 0x6e,
.group_count = ARRAY_SIZE(cannonlake_pch_h_community_0_groups),
.groups = cannonlake_pch_h_community_0_groups,
};
static const struct gpio_group *const cannonlake_pch_h_community_1_groups[] = {
&cannonlake_pch_h_group_c,
&cannonlake_pch_h_group_d,
&cannonlake_pch_h_group_g,
&cannonlake_pch_h_group_aza,
&cannonlake_pch_h_group_vgpio_0,
&cannonlake_pch_h_group_vgpio_1,
};
static const struct gpio_community cannonlake_pch_h_community_1 = {
.name = "------- GPIO Community 1 -------",
.pcr_port_id = 0x6d,
.group_count = ARRAY_SIZE(cannonlake_pch_h_community_1_groups),
.groups = cannonlake_pch_h_community_1_groups,
};
static const struct gpio_group *const cannonlake_pch_h_community_2_groups[] = {
&cannonlake_pch_h_group_gpd,
};
static const struct gpio_community cannonlake_pch_h_community_2 = {
.name = "------- GPIO Community 2 -------",
.pcr_port_id = 0x6c,
.group_count = ARRAY_SIZE(cannonlake_pch_h_community_2_groups),
.groups = cannonlake_pch_h_community_2_groups,
};
static const struct gpio_group *const cannonlake_pch_h_community_3_groups[] = {
&cannonlake_pch_h_group_k,
&cannonlake_pch_h_group_h,
&cannonlake_pch_h_group_e,
&cannonlake_pch_h_group_f,
&cannonlake_pch_h_group_spi,
};
static const struct gpio_community cannonlake_pch_h_community_3 = {
.name = "------- GPIO Community 3 -------",
.pcr_port_id = 0x6b,
.group_count = ARRAY_SIZE(cannonlake_pch_h_community_3_groups),
.groups = cannonlake_pch_h_community_3_groups,
};
static const struct gpio_group *const cannonlake_pch_h_community_4_groups[] = {
&cannonlake_pch_h_group_i,
&cannonlake_pch_h_group_j,
};
static const struct gpio_community cannonlake_pch_h_community_4 = {
.name = "------- GPIO Community 4 -------",
.pcr_port_id = 0x6a,
.group_count = ARRAY_SIZE(cannonlake_pch_h_community_4_groups),
.groups = cannonlake_pch_h_community_4_groups,
};
static const struct gpio_community *const cannonlake_pch_h_communities[] = {
&cannonlake_pch_h_community_0,
&cannonlake_pch_h_community_1,
&cannonlake_pch_h_community_2,
&cannonlake_pch_h_community_3,
&cannonlake_pch_h_community_4,
};
static const char *decode_pad_mode(const struct gpio_group *const group, static const char *decode_pad_mode(const struct gpio_group *const group,
const size_t pad, const uint32_t dw0) const size_t pad, const uint32_t dw0)
{ {
@ -1197,13 +1718,14 @@ static const char *decode_pad_mode(const struct gpio_group *const group,
} }
static void print_gpio_group(const uint8_t pid, size_t pad_cfg, static void print_gpio_group(const uint8_t pid, size_t pad_cfg,
const struct gpio_group *const group) const struct gpio_group *const group,
size_t pad_stepping)
{ {
size_t p; size_t p;
printf("%s\n", group->display); printf("%s\n", group->display);
for (p = 0; p < group->pad_count; ++p, pad_cfg += 8) { for (p = 0; p < group->pad_count; ++p, pad_cfg += pad_stepping) {
const uint32_t dw0 = read_pcr32(pid, pad_cfg); const uint32_t dw0 = read_pcr32(pid, pad_cfg);
const uint32_t dw1 = read_pcr32(pid, pad_cfg + 4); const uint32_t dw1 = read_pcr32(pid, pad_cfg + 4);
const char *const pad_name = const char *const pad_name =
@ -1216,7 +1738,8 @@ static void print_gpio_group(const uint8_t pid, size_t pad_cfg,
} }
} }
static void print_gpio_community(const struct gpio_community *const community) static void print_gpio_community(const struct gpio_community *const community,
size_t pad_stepping)
{ {
size_t group, pad_count; size_t group, pad_count;
size_t pad_cfg; /* offset in bytes under this communities PCR port */ size_t pad_cfg; /* offset in bytes under this communities PCR port */
@ -1236,8 +1759,9 @@ static void print_gpio_community(const struct gpio_community *const community)
for (group = 0; group < community->group_count; ++group) { for (group = 0; group < community->group_count; ++group) {
print_gpio_group(community->pcr_port_id, print_gpio_group(community->pcr_port_id,
pad_cfg, community->groups[group]); pad_cfg, community->groups[group],
pad_cfg += community->groups[group]->pad_count * 8; pad_stepping);
pad_cfg += community->groups[group]->pad_count * pad_stepping;
} }
} }
@ -1245,6 +1769,7 @@ void print_gpio_groups(struct pci_dev *const sb)
{ {
size_t community_count; size_t community_count;
const struct gpio_community *const *communities; const struct gpio_community *const *communities;
size_t pad_stepping = 8;
switch (sb->device_id) { switch (sb->device_id) {
case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_B150:
@ -1273,6 +1798,21 @@ void print_gpio_groups(struct pci_dev *const sb)
communities = apl_communities; communities = apl_communities;
pcr_init(sb); pcr_init(sb);
break; break;
case PCI_DEVICE_ID_INTEL_H310:
case PCI_DEVICE_ID_INTEL_H370:
case PCI_DEVICE_ID_INTEL_Z390:
case PCI_DEVICE_ID_INTEL_Q370:
case PCI_DEVICE_ID_INTEL_B360:
case PCI_DEVICE_ID_INTEL_C246:
case PCI_DEVICE_ID_INTEL_C242:
case PCI_DEVICE_ID_INTEL_QM370:
case PCI_DEVICE_ID_INTEL_HM370:
case PCI_DEVICE_ID_INTEL_CM246:
community_count = ARRAY_SIZE(cannonlake_pch_h_communities);
communities = cannonlake_pch_h_communities;
pad_stepping = 16;
pcr_init(sb);
break;
default: default:
return; return;
} }
@ -1280,5 +1820,5 @@ void print_gpio_groups(struct pci_dev *const sb)
printf("\n============= GPIOS =============\n\n"); printf("\n============= GPIOS =============\n\n");
for (; community_count; --community_count) for (; community_count; --community_count)
print_gpio_community(*communities++); print_gpio_community(*communities++, pad_stepping);
} }

10
util/inteltool/inteltool.c
View File

@ -250,6 +250,16 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM175, "HM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM175, "HM175" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM175, "QM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM175, "QM175" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM238, "CM238" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM238, "CM238" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H310, "H310" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H370, "H370" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z390, "Z390" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q370, "Q370" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B360, "B360" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C246, "C246" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C242, "C242" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM370, "QM370" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM370, "HM370" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM246, "CM246" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_MOBILE, "C8 Mobile"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_MOBILE, "C8 Mobile"},
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_DESKTOP, "C8 Desktop"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_DESKTOP, "C8 Desktop"},
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z87, "Z87"}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z87, "Z87"},

12
util/inteltool/inteltool.h
View File

@ -165,6 +165,18 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_HM175 0xa152 #define PCI_DEVICE_ID_INTEL_HM175 0xa152
#define PCI_DEVICE_ID_INTEL_QM175 0xa153 #define PCI_DEVICE_ID_INTEL_QM175 0xa153
#define PCI_DEVICE_ID_INTEL_CM238 0xa154 #define PCI_DEVICE_ID_INTEL_CM238 0xa154
#define PCI_DEVICE_ID_INTEL_H310 0xa303
#define PCI_DEVICE_ID_INTEL_H370 0xa304
#define PCI_DEVICE_ID_INTEL_Z390 0xa305
#define PCI_DEVICE_ID_INTEL_Q370 0xa306
#define PCI_DEVICE_ID_INTEL_B360 0xa308
#define PCI_DEVICE_ID_INTEL_C246 0xa309
#define PCI_DEVICE_ID_INTEL_C242 0xa30a
#define PCI_DEVICE_ID_INTEL_QM370 0xa30c
#define PCI_DEVICE_ID_INTEL_HM370 0xa30d
#define PCI_DEVICE_ID_INTEL_CM246 0xa30e
#define PCI_DEVICE_ID_INTEL_82810 0x7120 #define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122 #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124 #define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124

76
util/inteltool/pcr.c
View File

@ -71,6 +71,8 @@ void pcr_init(struct pci_dev *const sb)
bool error_exit = false; bool error_exit = false;
bool p2sb_revealed = false; bool p2sb_revealed = false;
struct pci_dev *p2sb; struct pci_dev *p2sb;
bool use_p2sb = true;
pciaddr_t sbbar_phys;
if (sbbar) if (sbbar)
return; return;
@ -103,38 +105,54 @@ void pcr_init(struct pci_dev *const sb)
case PCI_DEVICE_ID_INTEL_APL_LPC: case PCI_DEVICE_ID_INTEL_APL_LPC:
p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0); p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0);
break; break;
case PCI_DEVICE_ID_INTEL_H310:
case PCI_DEVICE_ID_INTEL_H370:
case PCI_DEVICE_ID_INTEL_Z390:
case PCI_DEVICE_ID_INTEL_Q370:
case PCI_DEVICE_ID_INTEL_B360:
case PCI_DEVICE_ID_INTEL_C246:
case PCI_DEVICE_ID_INTEL_C242:
case PCI_DEVICE_ID_INTEL_QM370:
case PCI_DEVICE_ID_INTEL_HM370:
case PCI_DEVICE_ID_INTEL_CM246:
sbbar_phys = 0xfd000000;
use_p2sb = false;
break;
default: default:
perror("Unknown LPC device."); perror("Unknown LPC device.");
exit(1); exit(1);
} }
if (!p2sb) { if (use_p2sb) {
perror("Can't allocate device node for P2SB."); if (!p2sb) {
exit(1); perror("Can't allocate device node for P2SB.");
}
/* do not fill bases here, libpci refuses to refill later */
pci_fill_info(p2sb, PCI_FILL_IDENT);
if (p2sb->vendor_id == 0xffff && p2sb->device_id == 0xffff) {
printf("Trying to reveal Primary to Sideband Bridge "
"(P2SB),\nlet's hope the OS doesn't mind... ");
/* Do not use pci_write_long(). Bytes
surrounding 0xe0 must be maintained. */
pci_write_byte(p2sb, 0xe0 + 1, 0);
pci_fill_info(p2sb, PCI_FILL_IDENT | PCI_FILL_RESCAN);
if (p2sb->vendor_id != 0xffff ||
p2sb->device_id != 0xffff) {
printf("done.\n");
p2sb_revealed = true;
} else {
printf("failed.\n");
exit(1); exit(1);
} }
}
pci_fill_info(p2sb, PCI_FILL_BASES | PCI_FILL_CLASS);
const pciaddr_t sbbar_phys = p2sb->base_addr[0] & ~0xfULL; /* do not fill bases here, libpci refuses to refill later */
pci_fill_info(p2sb, PCI_FILL_IDENT);
if (p2sb->vendor_id == 0xffff && p2sb->device_id == 0xffff) {
printf("Trying to reveal Primary to Sideband Bridge "
"(P2SB),\nlet's hope the OS doesn't mind... ");
/* Do not use pci_write_long(). Bytes
surrounding 0xe0 must be maintained. */
pci_write_byte(p2sb, 0xe0 + 1, 0);
pci_fill_info(p2sb, PCI_FILL_IDENT | PCI_FILL_RESCAN);
if (p2sb->vendor_id != 0xffff ||
p2sb->device_id != 0xffff) {
printf("done.\n");
p2sb_revealed = true;
} else {
printf("failed.\n");
exit(1);
}
}
pci_fill_info(p2sb, PCI_FILL_BASES | PCI_FILL_CLASS);
sbbar_phys = p2sb->base_addr[0] & ~0xfULL;
}
printf("SBREG_BAR = 0x%08"PRIx64" (MEM)\n\n", (uint64_t)sbbar_phys); printf("SBREG_BAR = 0x%08"PRIx64" (MEM)\n\n", (uint64_t)sbbar_phys);
sbbar = map_physical(sbbar_phys, SBBAR_SIZE); sbbar = map_physical(sbbar_phys, SBBAR_SIZE);
if (sbbar == NULL) { if (sbbar == NULL) {
@ -142,11 +160,13 @@ void pcr_init(struct pci_dev *const sb)
error_exit = true; error_exit = true;
} }
if (p2sb_revealed) { if (use_p2sb) {
printf("Hiding Primary to Sideband Bridge (P2SB).\n"); if (p2sb_revealed) {
pci_write_byte(p2sb, 0xe0 + 1, 1); printf("Hiding Primary to Sideband Bridge (P2SB).\n");
pci_write_byte(p2sb, 0xe0 + 1, 1);
}
pci_free_dev(p2sb);
} }
pci_free_dev(p2sb);
if (error_exit) if (error_exit)
exit(1); exit(1);