sb/intel/spi: Drop CAR_GLOBAL_MIGRATION
Change-Id: I693cf494522c3bc1e1697a09be3e98fcb6db634d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
5b0db35e0d
commit
7255610d9f
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@ -18,7 +18,6 @@
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#define __SIMPLE_DEVICE__
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/* This file is derived from the flashrom project. */
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#include <arch/early_variables.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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@ -112,7 +111,7 @@ struct ich_spi_controller {
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uint8_t fpr_max;
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};
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static struct ich_spi_controller g_cntlr CAR_GLOBAL;
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static struct ich_spi_controller g_cntlr;
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enum {
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SPIS_SCIP = 0x0001,
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@ -257,14 +256,13 @@ static void read_reg(const void *src, void *value, uint32_t size)
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static void ich_set_bbar(uint32_t minaddr)
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{
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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const uint32_t bbar_mask = 0x00ffff00;
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uint32_t ichspi_bbar;
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minaddr &= bbar_mask;
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ichspi_bbar = readl_(cntlr->bbar) & ~bbar_mask;
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ichspi_bbar = readl_(g_cntlr.bbar) & ~bbar_mask;
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ichspi_bbar |= minaddr;
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writel_(ichspi_bbar, cntlr->bbar);
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writel_(ichspi_bbar, g_cntlr.bbar);
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}
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#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
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@ -298,7 +296,6 @@ static void *get_spi_bar(pci_devfn_t dev)
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void spi_init(void)
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{
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint8_t bios_cntl;
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struct ich9_spi_regs *ich9_spi;
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struct ich7_spi_regs *ich7_spi;
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@ -308,42 +305,42 @@ void spi_init(void)
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if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
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ich7_spi = get_spi_bar(dev);
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cntlr->ich7_spi = ich7_spi;
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cntlr->opmenu = ich7_spi->opmenu;
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cntlr->menubytes = sizeof(ich7_spi->opmenu);
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cntlr->optype = &ich7_spi->optype;
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cntlr->addr = &ich7_spi->spia;
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cntlr->data = (uint8_t *)ich7_spi->spid;
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cntlr->databytes = sizeof(ich7_spi->spid);
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cntlr->status = (uint8_t *)&ich7_spi->spis;
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cntlr->control = &ich7_spi->spic;
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cntlr->bbar = &ich7_spi->bbar;
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cntlr->preop = &ich7_spi->preop;
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cntlr->fpr = &ich7_spi->pbr[0];
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cntlr->fpr_max = 3;
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g_cntlr.ich7_spi = ich7_spi;
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g_cntlr.opmenu = ich7_spi->opmenu;
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g_cntlr.menubytes = sizeof(ich7_spi->opmenu);
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g_cntlr.optype = &ich7_spi->optype;
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g_cntlr.addr = &ich7_spi->spia;
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g_cntlr.data = (uint8_t *)ich7_spi->spid;
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g_cntlr.databytes = sizeof(ich7_spi->spid);
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g_cntlr.status = (uint8_t *)&ich7_spi->spis;
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g_cntlr.control = &ich7_spi->spic;
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g_cntlr.bbar = &ich7_spi->bbar;
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g_cntlr.preop = &ich7_spi->preop;
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g_cntlr.fpr = &ich7_spi->pbr[0];
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g_cntlr.fpr_max = 3;
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} else {
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ich9_spi = get_spi_bar(dev);
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cntlr->ich9_spi = ich9_spi;
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g_cntlr.ich9_spi = ich9_spi;
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hsfs = readw_(&ich9_spi->hsfs);
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cntlr->hsfs = hsfs;
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cntlr->opmenu = ich9_spi->opmenu;
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cntlr->menubytes = sizeof(ich9_spi->opmenu);
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cntlr->optype = &ich9_spi->optype;
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cntlr->addr = &ich9_spi->faddr;
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cntlr->data = (uint8_t *)ich9_spi->fdata;
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cntlr->databytes = sizeof(ich9_spi->fdata);
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cntlr->status = &ich9_spi->ssfs;
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cntlr->control = (uint16_t *)ich9_spi->ssfc;
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cntlr->bbar = &ich9_spi->bbar;
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cntlr->preop = &ich9_spi->preop;
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cntlr->fpr = &ich9_spi->pr[0];
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cntlr->fpr_max = 5;
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g_cntlr.hsfs = hsfs;
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g_cntlr.opmenu = ich9_spi->opmenu;
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g_cntlr.menubytes = sizeof(ich9_spi->opmenu);
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g_cntlr.optype = &ich9_spi->optype;
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g_cntlr.addr = &ich9_spi->faddr;
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g_cntlr.data = (uint8_t *)ich9_spi->fdata;
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g_cntlr.databytes = sizeof(ich9_spi->fdata);
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g_cntlr.status = &ich9_spi->ssfs;
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g_cntlr.control = (uint16_t *)ich9_spi->ssfc;
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g_cntlr.bbar = &ich9_spi->bbar;
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g_cntlr.preop = &ich9_spi->preop;
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g_cntlr.fpr = &ich9_spi->pr[0];
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g_cntlr.fpr_max = 5;
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if (cntlr->hsfs & HSFS_FDV) {
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if (g_cntlr.hsfs & HSFS_FDV) {
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writel_(4, &ich9_spi->fdoc);
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cntlr->flmap0 = readl_(&ich9_spi->fdod);
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g_cntlr.flmap0 = readl_(&ich9_spi->fdod);
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writel_(0x1000, &ich9_spi->fdoc);
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cntlr->flcomp = readl_(&ich9_spi->fdod);
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g_cntlr.flcomp = readl_(&ich9_spi->fdod);
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}
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}
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@ -360,11 +357,10 @@ void spi_init(void)
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static int spi_locked(void)
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{
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struct ich_spi_controller *cntlr = &g_cntlr;
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if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
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return !!(readw_(&cntlr->ich7_spi->spis) & HSFS_FLOCKDN);
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return !!(readw_(&g_cntlr.ich7_spi->spis) & HSFS_FLOCKDN);
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} else {
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return !!(readw_(&cntlr->ich9_spi->hsfs) & HSFS_FLOCKDN);
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return !!(readw_(&g_cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN);
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}
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}
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@ -433,7 +429,6 @@ static void spi_setup_type(spi_transaction *trans)
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static int spi_setup_opcode(spi_transaction *trans)
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{
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint16_t optypes;
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uint8_t opmenu[MENU_BYTES];
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@ -441,10 +436,10 @@ static int spi_setup_opcode(spi_transaction *trans)
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spi_use_out(trans, 1);
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if (!spi_locked()) {
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/* The lock is off, so just use index 0. */
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writeb_(trans->opcode, cntlr->opmenu);
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optypes = readw_(cntlr->optype);
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writeb_(trans->opcode, g_cntlr.opmenu);
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optypes = readw_(g_cntlr.optype);
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optypes = (optypes & 0xfffc) | (trans->type & 0x3);
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writew_(optypes, cntlr->optype);
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writew_(optypes, g_cntlr.optype);
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return 0;
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}
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@ -456,7 +451,7 @@ static int spi_setup_opcode(spi_transaction *trans)
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if (trans->opcode == SPI_OPCODE_WREN)
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return 0;
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read_reg(cntlr->opmenu, opmenu, sizeof(opmenu));
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read_reg(g_cntlr.opmenu, opmenu, sizeof(opmenu));
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for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) {
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if (opmenu[opcode_index] == trans->opcode)
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break;
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@ -468,7 +463,7 @@ static int spi_setup_opcode(spi_transaction *trans)
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return -1;
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}
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optypes = readw_(cntlr->optype);
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optypes = readw_(g_cntlr.optype);
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optype = (optypes >> (opcode_index * 2)) & 0x3;
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if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
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optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
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@ -513,15 +508,14 @@ static int spi_setup_offset(spi_transaction *trans)
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*/
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static int ich_status_poll(u16 bitmask, int wait_til_set)
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{
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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int timeout = 600000; /* This will result in 6 seconds */
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u16 status = 0;
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while (timeout--) {
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status = readw_(cntlr->status);
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status = readw_(g_cntlr.status);
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if (wait_til_set ^ ((status & bitmask) == 0)) {
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if (wait_til_set)
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writew_((status & bitmask), cntlr->status);
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writew_((status & bitmask), g_cntlr.status);
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return status;
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}
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udelay(10);
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@ -534,16 +528,14 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
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static int spi_is_multichip(void)
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{
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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if (!(cntlr->hsfs & HSFS_FDV))
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if (!(g_cntlr.hsfs & HSFS_FDV))
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return 0;
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return !!((cntlr->flmap0 >> 8) & 3);
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return !!((g_cntlr.flmap0 >> 8) & 3);
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}
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static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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size_t bytesout, void *din, size_t bytesin)
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{
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint16_t control;
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int16_t opcode_index;
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int with_address;
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@ -569,7 +561,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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if (ich_status_poll(SPIS_SCIP, 0) == -1)
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return -1;
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writew_(SPIS_CDS | SPIS_FCERR, cntlr->status);
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writew_(SPIS_CDS | SPIS_FCERR, g_cntlr.status);
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spi_setup_type(&trans);
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if ((opcode_index = spi_setup_opcode(&trans)) < 0)
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@ -584,7 +576,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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* issuing a transaction between WREN and DATA.
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*/
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if (!spi_locked())
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writew_(trans.opcode, cntlr->preop);
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writew_(trans.opcode, g_cntlr.preop);
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return 0;
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}
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@ -592,13 +584,13 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
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/* Issue atomic preop cycle if needed */
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if (readw_(cntlr->preop))
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if (readw_(g_cntlr.preop))
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control |= SPIC_ACS;
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if (!trans.bytesout && !trans.bytesin) {
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/* SPI addresses are 24 bit only */
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if (with_address)
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writel_(trans.offset & 0x00FFFFFF, cntlr->addr);
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writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr);
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/*
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* This is a 'no data' command (like Write Enable), its
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@ -606,7 +598,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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* spi_setup_opcode() above. Tell the chip to send the
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* command.
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*/
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writew_(control, cntlr->control);
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writew_(control, g_cntlr.control);
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/* wait for the result */
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status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
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@ -628,7 +620,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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* and followed by other SPI commands, and this sequence is controlled
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* by the SPI chip driver.
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*/
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if (trans.bytesout > cntlr->databytes) {
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if (trans.bytesout > g_cntlr.databytes) {
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printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
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" spi_crop_chunk()?\n");
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return -1;
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@ -642,28 +634,28 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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uint32_t data_length;
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/* SPI addresses are 24 bit only */
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writel_(trans.offset & 0x00FFFFFF, cntlr->addr);
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writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr);
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if (trans.bytesout)
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data_length = min(trans.bytesout, cntlr->databytes);
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data_length = min(trans.bytesout, g_cntlr.databytes);
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else
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data_length = min(trans.bytesin, cntlr->databytes);
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data_length = min(trans.bytesin, g_cntlr.databytes);
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/* Program data into FDATA0 to N */
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if (trans.bytesout) {
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write_reg(trans.out, cntlr->data, data_length);
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write_reg(trans.out, g_cntlr.data, data_length);
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spi_use_out(&trans, data_length);
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if (with_address)
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trans.offset += data_length;
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}
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/* Add proper control fields' values */
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control &= ~((cntlr->databytes - 1) << 8);
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control &= ~((g_cntlr.databytes - 1) << 8);
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control |= SPIC_DS;
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control |= (data_length - 1) << 8;
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/* write it */
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writew_(control, cntlr->control);
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writew_(control, g_cntlr.control);
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/* Wait for Cycle Done Status or Flash Cycle Error. */
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status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
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@ -676,7 +668,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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}
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if (trans.bytesin) {
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read_reg(cntlr->data, trans.in, data_length);
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read_reg(g_cntlr.data, trans.in, data_length);
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spi_use_in(&trans, data_length);
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if (with_address)
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trans.offset += data_length;
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@ -685,7 +677,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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spi_xfer_exit:
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/* Clear atomic preop now that xfer is done */
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writew_(0, cntlr->preop);
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writew_(0, g_cntlr.preop);
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return 0;
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}
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@ -693,10 +685,9 @@ spi_xfer_exit:
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/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
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static void ich_hwseq_set_addr(uint32_t addr)
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{
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF;
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uint32_t addr_old = readl_(&g_cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
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writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr);
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writel_((addr & 0x01FFFFFF) | addr_old, &g_cntlr.ich9_spi->faddr);
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}
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/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
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@ -706,22 +697,21 @@ static void ich_hwseq_set_addr(uint32_t addr)
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static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
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unsigned int len)
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{
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struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
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uint16_t hsfs;
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uint32_t addr;
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timeout /= 8; /* scale timeout duration to counter */
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while ((((hsfs = readw_(&cntlr->ich9_spi->hsfs)) &
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while ((((hsfs = readw_(&g_cntlr.ich9_spi->hsfs)) &
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(HSFS_FDONE | HSFS_FCERR)) == 0) &&
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--timeout) {
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udelay(8);
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}
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writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs);
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writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
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if (!timeout) {
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uint16_t hsfc;
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addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF;
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hsfc = readw_(&cntlr->ich9_spi->hsfc);
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addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF;
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hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
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printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
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"0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
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addr, addr + len - 1, addr, len - 1,
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@ -731,8 +721,8 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
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if (hsfs & HSFS_FCERR) {
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uint16_t hsfc;
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addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF;
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hsfc = readw_(&cntlr->ich9_spi->hsfc);
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addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF;
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hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
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printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
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"0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
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addr, addr + len - 1, addr, len - 1,
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@ -746,7 +736,6 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
|
|||
static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
|
||||
size_t len)
|
||||
{
|
||||
struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
|
||||
u32 start, end, erase_size;
|
||||
int ret;
|
||||
uint16_t hsfc;
|
||||
|
|
@ -769,17 +758,17 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
|
|||
|
||||
while (offset < end) {
|
||||
/* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
|
||||
writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs);
|
||||
writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
|
||||
|
||||
ich_hwseq_set_addr(offset);
|
||||
|
||||
offset += erase_size;
|
||||
|
||||
hsfc = readw_(&cntlr->ich9_spi->hsfc);
|
||||
hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
|
||||
hsfc &= ~HSFC_FCYCLE; /* clear operation */
|
||||
hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
|
||||
hsfc |= HSFC_FGO; /* start */
|
||||
writew_(hsfc, &cntlr->ich9_spi->hsfc);
|
||||
writew_(hsfc, &g_cntlr.ich9_spi->hsfc);
|
||||
if (ich_hwseq_wait_for_cycle_complete(timeout, len)) {
|
||||
printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
|
||||
ret = -1;
|
||||
|
|
@ -796,13 +785,12 @@ out:
|
|||
|
||||
static void ich_read_data(uint8_t *data, int len)
|
||||
{
|
||||
struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
|
||||
int i;
|
||||
uint32_t temp32 = 0;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if ((i % 4) == 0)
|
||||
temp32 = readl_(cntlr->data + i);
|
||||
temp32 = readl_(g_cntlr.data + i);
|
||||
|
||||
data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
|
||||
}
|
||||
|
|
@ -811,7 +799,6 @@ static void ich_read_data(uint8_t *data, int len)
|
|||
static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
|
||||
void *buf)
|
||||
{
|
||||
struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
|
||||
uint16_t hsfc;
|
||||
uint16_t timeout = 100 * 60;
|
||||
uint8_t block_len;
|
||||
|
|
@ -825,20 +812,20 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
|
|||
}
|
||||
|
||||
/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
|
||||
writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs);
|
||||
writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
|
||||
|
||||
while (len > 0) {
|
||||
block_len = min(len, cntlr->databytes);
|
||||
block_len = min(len, g_cntlr.databytes);
|
||||
if (block_len > (~addr & 0xff))
|
||||
block_len = (~addr & 0xff) + 1;
|
||||
ich_hwseq_set_addr(addr);
|
||||
hsfc = readw_(&cntlr->ich9_spi->hsfc);
|
||||
hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
|
||||
hsfc &= ~HSFC_FCYCLE; /* set read operation */
|
||||
hsfc &= ~HSFC_FDBC; /* clear byte count */
|
||||
/* set byte count */
|
||||
hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
|
||||
hsfc |= HSFC_FGO; /* start */
|
||||
writew_(hsfc, &cntlr->ich9_spi->hsfc);
|
||||
writew_(hsfc, &g_cntlr.ich9_spi->hsfc);
|
||||
|
||||
if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
|
||||
return 1;
|
||||
|
|
@ -857,7 +844,6 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
|
|||
*/
|
||||
static void ich_fill_data(const uint8_t *data, int len)
|
||||
{
|
||||
struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
|
||||
uint32_t temp32 = 0;
|
||||
int i;
|
||||
|
||||
|
|
@ -871,17 +857,16 @@ static void ich_fill_data(const uint8_t *data, int len)
|
|||
temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
|
||||
|
||||
if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
|
||||
writel_(temp32, cntlr->data + (i - (i % 4)));
|
||||
writel_(temp32, g_cntlr.data + (i - (i % 4)));
|
||||
}
|
||||
i--;
|
||||
if ((i % 4) != 3) /* Write remaining data to regs. */
|
||||
writel_(temp32, cntlr->data + (i - (i % 4)));
|
||||
writel_(temp32, g_cntlr.data + (i - (i % 4)));
|
||||
}
|
||||
|
||||
static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
|
||||
const void *buf)
|
||||
{
|
||||
struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
|
||||
uint16_t hsfc;
|
||||
uint16_t timeout = 100 * 60;
|
||||
uint8_t block_len;
|
||||
|
|
@ -895,24 +880,24 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
|
|||
}
|
||||
|
||||
/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
|
||||
writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs);
|
||||
writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
|
||||
|
||||
while (len > 0) {
|
||||
block_len = min(len, cntlr->databytes);
|
||||
block_len = min(len, g_cntlr.databytes);
|
||||
if (block_len > (~addr & 0xff))
|
||||
block_len = (~addr & 0xff) + 1;
|
||||
|
||||
ich_hwseq_set_addr(addr);
|
||||
|
||||
ich_fill_data(buf, block_len);
|
||||
hsfc = readw_(&cntlr->ich9_spi->hsfc);
|
||||
hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
|
||||
hsfc &= ~HSFC_FCYCLE; /* clear operation */
|
||||
hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
|
||||
hsfc &= ~HSFC_FDBC; /* clear byte count */
|
||||
/* set byte count */
|
||||
hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
|
||||
hsfc |= HSFC_FGO; /* start */
|
||||
writew_(hsfc, &cntlr->ich9_spi->hsfc);
|
||||
writew_(hsfc, &g_cntlr.ich9_spi->hsfc);
|
||||
|
||||
if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) {
|
||||
printk(BIOS_ERR, "SF: write failure at %x\n",
|
||||
|
|
@ -937,7 +922,6 @@ static const struct spi_flash_ops spi_flash_ops = {
|
|||
static int spi_flash_programmer_probe(const struct spi_slave *spi,
|
||||
struct spi_flash *flash)
|
||||
{
|
||||
struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
|
||||
|
||||
if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
|
||||
return spi_flash_generic_probe(spi, flash);
|
||||
|
|
@ -950,7 +934,7 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi,
|
|||
flash->name = "Opaque HW-sequencing";
|
||||
|
||||
ich_hwseq_set_addr(0);
|
||||
switch ((cntlr->hsfs >> 3) & 3) {
|
||||
switch ((g_cntlr.hsfs >> 3) & 3) {
|
||||
case 0:
|
||||
flash->sector_size = 256;
|
||||
break;
|
||||
|
|
@ -965,12 +949,12 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi,
|
|||
break;
|
||||
}
|
||||
|
||||
flash->size = 1 << (19 + (cntlr->flcomp & 7));
|
||||
flash->size = 1 << (19 + (g_cntlr.flcomp & 7));
|
||||
|
||||
flash->ops = &spi_flash_ops;
|
||||
|
||||
if ((cntlr->hsfs & HSFS_FDV) && ((cntlr->flmap0 >> 8) & 3))
|
||||
flash->size += 1 << (19 + ((cntlr->flcomp >> 3) & 7));
|
||||
if ((g_cntlr.hsfs & HSFS_FDV) && ((g_cntlr.flmap0 >> 8) & 3))
|
||||
flash->size += 1 << (19 + ((g_cntlr.flcomp >> 3) & 7));
|
||||
printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1017,7 +1001,6 @@ static int spi_flash_protect(const struct spi_flash *flash,
|
|||
const struct region *region,
|
||||
const enum ctrlr_prot_type type)
|
||||
{
|
||||
struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
|
||||
u32 start = region_offset(region);
|
||||
u32 end = start + region_sz(region) - 1;
|
||||
u32 reg;
|
||||
|
|
@ -1025,16 +1008,16 @@ static int spi_flash_protect(const struct spi_flash *flash,
|
|||
int fpr;
|
||||
uint32_t *fpr_base;
|
||||
|
||||
fpr_base = cntlr->fpr;
|
||||
fpr_base = g_cntlr.fpr;
|
||||
|
||||
/* Find first empty FPR */
|
||||
for (fpr = 0; fpr < cntlr->fpr_max; fpr++) {
|
||||
for (fpr = 0; fpr < g_cntlr.fpr_max; fpr++) {
|
||||
reg = read32(&fpr_base[fpr]);
|
||||
if (reg == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (fpr == cntlr->fpr_max) {
|
||||
if (fpr == g_cntlr.fpr_max) {
|
||||
printk(BIOS_ERR, "ERROR: No SPI FPR free!\n");
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -1075,7 +1058,6 @@ static int spi_flash_protect(const struct spi_flash *flash,
|
|||
|
||||
void spi_finalize_ops(void)
|
||||
{
|
||||
struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
|
||||
u16 spi_opprefix;
|
||||
u16 optype = 0;
|
||||
struct intel_swseq_spi_config spi_config_default = {
|
||||
|
|
@ -1124,12 +1106,12 @@ void spi_finalize_ops(void)
|
|||
|
||||
spi_opprefix = spi_config->opprefixes[0]
|
||||
| (spi_config->opprefixes[1] << 8);
|
||||
writew_(spi_opprefix, cntlr->preop);
|
||||
writew_(spi_opprefix, g_cntlr.preop);
|
||||
for (i = 0; i < ARRAY_SIZE(spi_config->ops); i++) {
|
||||
optype |= (spi_config->ops[i].type & 3) << (i * 2);
|
||||
writeb_(spi_config->ops[i].op, &cntlr->opmenu[i]);
|
||||
writeb_(spi_config->ops[i].op, &g_cntlr.opmenu[i]);
|
||||
}
|
||||
writew_(optype, cntlr->optype);
|
||||
writew_(optype, g_cntlr.optype);
|
||||
}
|
||||
|
||||
__weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config)
|
||||
|
|
|
|||
Loading…
Reference in New Issue