From 72616b3813382d8eeaaf97d86ebc90e784c5bad5 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Fri, 5 Feb 2021 16:48:42 -0700 Subject: [PATCH] soc/amd/cezanne: Add verstage support Setup the config required to support verstage. The offsets are the same as picasso. Signed-off-by: Raul E Rangel Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50342 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/cezanne/Kconfig | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 530b4e7992..10c085e018 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -109,10 +109,31 @@ config FSP_TEMP_RAM_SIZE help The amount of coreboot-allocated heap and stack usage by the FSP. +config VERSTAGE_ADDR + hex + depends on VBOOT_SEPARATE_VERSTAGE + default 0x2140000 + help + Sets the address in DRAM where verstage should be loaded if running + as a separate stage on x86. + +config VERSTAGE_SIZE + hex + depends on VBOOT_SEPARATE_VERSTAGE + default 0x80000 + help + Sets the size of DRAM allocation for verstage in linker script if + running as a separate stage on x86. + config RAMBASE hex default 0x10000000 +config RO_REGION_ONLY + string + depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A + default "apu/amdfw" + config CPU_ADDR_BITS int default 48