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cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMER 

Leftover from using UDELAY_LAPIC on these platforms.

Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2021-06-05 15:41:09 +03:00
parent 7aea15aa6b
commit 7261b5ade5
7 changed files with 0 additions and 33 deletions
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15
src/cpu/intel/model_1067x/model_1067x_init.c
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@ -12,18 +12,6 @@
#include "chip.h" #include "chip.h"
static void init_timer(void)
{
/* Set the APIC timer to no interrupts and periodic mode */
lapic_write(LAPIC_LVTT, (1 << 17) | (1 << 16) | (0 << 12) | (0 << 0));
/* Set the divider to 1, no divider */
lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
/* Set the initial counter to 0xffffffff */
lapic_write(LAPIC_TMICT, 0xffffffff);
}
#define MSR_BBL_CR_CTL3 0x11e #define MSR_BBL_CR_CTL3 0x11e
static void configure_c_states(const int quad) static void configure_c_states(const int quad)
@ -271,9 +259,6 @@ static void model_1067x_init(struct device *cpu)
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */
setup_lapic(); setup_lapic();
/* Initialize the APIC timer */
init_timer();
/* Configure C States */ /* Configure C States */
configure_c_states(quad); configure_c_states(quad);

3
src/northbridge/intel/gm45/romstage.c
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@ -5,7 +5,6 @@
#include <console/console.h> #include <console/console.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <cpu/x86/lapic.h>
#include <arch/romstage.h> #include <arch/romstage.h>
#include <northbridge/intel/gm45/gm45.h> #include <northbridge/intel/gm45/gm45.h>
#include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/i82801ix/i82801ix.h>
@ -42,8 +41,6 @@ void mainboard_romstage_entry(void)
/* basic northbridge setup, including MMCONF BAR */ /* basic northbridge setup, including MMCONF BAR */
gm45_early_init(); gm45_early_init();
enable_lapic();
/* First, run everything needed for console output. */ /* First, run everything needed for console output. */
i82801ix_early_init(); i82801ix_early_init();
setup_pch_gpios(&mainboard_gpio_map); setup_pch_gpios(&mainboard_gpio_map);

3
src/northbridge/intel/haswell/romstage.c
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@ -4,7 +4,6 @@
#include <console/console.h> #include <console/console.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <elog.h> #include <elog.h>
#include <cpu/x86/lapic.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <security/intel/txt/txt.h> #include <security/intel/txt/txt.h>
#include <security/intel/txt/txt_register.h> #include <security/intel/txt/txt_register.h>
@ -20,8 +19,6 @@ void __weak mb_late_romstage_setup(void)
/* The romstage entry point for this platform is not mainboard-specific, hence the name */ /* The romstage entry point for this platform is not mainboard-specific, hence the name */
void mainboard_romstage_entry(void) void mainboard_romstage_entry(void)
{ {
enable_lapic();
early_pch_init(); early_pch_init();
/* Perform some early chipset initialization required /* Perform some early chipset initialization required

3
src/northbridge/intel/i945/romstage.c
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@ -2,7 +2,6 @@
#include <stdint.h> #include <stdint.h>
#include <cf9_reset.h> #include <cf9_reset.h>
#include <cpu/x86/lapic.h>
#include <arch/romstage.h> #include <arch/romstage.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h> #include <northbridge/intel/i945/raminit.h>
@ -30,8 +29,6 @@ void mainboard_romstage_entry(void)
int s3resume = 0; int s3resume = 0;
u8 spd_map[4] = {}; u8 spd_map[4] = {};
enable_lapic();
mainboard_lpc_decode(); mainboard_lpc_decode();
if (mchbar_read16(SSKPD) == 0xcafe) { if (mchbar_read16(SSKPD) == 0xcafe) {

3
src/northbridge/intel/ironlake/romstage.c
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@ -5,7 +5,6 @@
#include <console/console.h> #include <console/console.h>
#include <cf9_reset.h> #include <cf9_reset.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <cpu/x86/lapic.h>
#include <timestamp.h> #include <timestamp.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include "ironlake.h" #include "ironlake.h"
@ -27,8 +26,6 @@ void mainboard_romstage_entry(void)
int s3resume = 0; int s3resume = 0;
u8 spd_addrmap[4] = {}; u8 spd_addrmap[4] = {};
enable_lapic();
/* TODO, make this configurable */ /* TODO, make this configurable */
ironlake_early_initialization(IRONLAKE_MOBILE); ironlake_early_initialization(IRONLAKE_MOBILE);

3
src/northbridge/intel/pineview/romstage.c
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@ -9,7 +9,6 @@
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/common/pmclib.h>
#include <arch/romstage.h> #include <arch/romstage.h>
#include <cpu/x86/lapic.h>
#include "raminit.h" #include "raminit.h"
#include "pineview.h" #include "pineview.h"
@ -31,8 +30,6 @@ void mainboard_romstage_entry(void)
int boot_path, cbmem_was_initted; int boot_path, cbmem_was_initted;
int s3resume = 0; int s3resume = 0;
enable_lapic();
/* Do some early chipset init, necessary for RAM init to work */ /* Do some early chipset init, necessary for RAM init to work */
i82801gx_early_init(); i82801gx_early_init();
pineview_early_init(); pineview_early_init();

3
src/northbridge/intel/sandybridge/romstage.c
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@ -3,7 +3,6 @@
#include <console/console.h> #include <console/console.h>
#include <cf9_reset.h> #include <cf9_reset.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <cpu/x86/lapic.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include "sandybridge.h" #include "sandybridge.h"
#include <arch/romstage.h> #include <arch/romstage.h>
@ -54,8 +53,6 @@ void mainboard_romstage_entry(void)
if (mchbar_read16(SSKPD_HI) == 0xcafe) if (mchbar_read16(SSKPD_HI) == 0xcafe)
system_reset(); system_reset();
enable_lapic();
/* Init LPC, GPIO, BARs, disable watchdog ... */ /* Init LPC, GPIO, BARs, disable watchdog ... */
early_pch_init(); early_pch_init();